Patents by Inventor Feng-Jia Shiu
Feng-Jia Shiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9917006Abstract: A method includes forming a patterned layer on a substrate having a first region and a second region being adjacent each other. The patterned layer includes first features in the first region. The second region is free of the patterned layer. The method further includes forming a material layer on the patterned layer and the substrate; forming a first guard ring disposed in the second region and surrounding the first features; forming a flowable-material (FM) layer over the material layer; forming a patterned resist layer over the FM layer, wherein the patterned resist layer includes a plurality of openings; and transferring the plurality of openings to the material layer.Type: GrantFiled: September 9, 2016Date of Patent: March 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chihy-Yuan Cheng, Chun-Chang Wu, Shun-Shing Yang, Ching-Sen Kuo, Feng-Jia Shiu, Chun-Chang Chen
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Publication number: 20170186808Abstract: A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.Type: ApplicationFiled: March 7, 2016Publication date: June 29, 2017Inventors: Wei-Chao Chiu, Chih-Chien Wang, Feng-Jia Shiu, Ching-Sen Kuo, Chun-Wei Chang, Kai Tzeng
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Publication number: 20160216613Abstract: A method provides an integrated circuit (IC) substrate having first and second alignment marks defined in a first pattern layer, and third and fourth alignment marks defined in a second pattern layer. The first and second alignment marks are illuminated, through a photomask, with a first light to determine a first layer alignment error including a first alignment error and a second alignment error. The first alignment error has more weight than the second alignment error in determining the first layer alignment error. The third and fourth alignment marks are illuminated with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to the fourth alignment mark. The third alignment error has more weight than the fourth alignment error in determining the second layer alignment error.Type: ApplicationFiled: April 4, 2016Publication date: July 28, 2016Inventors: Yu-Hsien Lin, Hung-Chang Hsieh, Feng-Jia Shiu, Chun-Yi Lee
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Patent number: 9304403Abstract: The present disclosure provides one embodiment of a lithography system for integrated circuit making. The system includes a substrate stage designed to secure a substrate and being operable to move the substrate; an alignment module that includes a tunable light source being operable to generate an infrared light with a wavelength tunable; and a detector to receive the light; and an exposing module integrated with the alignment module and designed to performing an exposing process to a resist layer coated on the substrate.Type: GrantFiled: January 2, 2013Date of Patent: April 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hsien Lin, Hung-Chang Hsieh, Feng-Jia Shiu, Chun-Yi Lee
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Patent number: 9196646Abstract: The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy.Type: GrantFiled: May 10, 2013Date of Patent: November 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Cheng Liu, Ching-Hung Cheng, Chien-Hsien Tseng, Chia-Hao Hsu, Feng-Jia Shiu, Shou-Gwo Wuu
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Patent number: 9153620Abstract: A method for manufacturing the image sensor device is provided. The method includes depositing a first dielectric layer over a back surface of a substrate, forming a ridge over the first dielectric layer, depositing a second dielectric layer over the first dielectric layer, including filling in a space between two adjacent ridges. The method also includes removing the ridge to form a trench in the second dielectric layer and forming a metal grid in the trench.Type: GrantFiled: March 3, 2014Date of Patent: October 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Wang, Chihy-Yuan Cheng, Chuan-Ling Wu, Chun-Chang Chen, Wang-Pen Mo, Feng-Jia Shiu
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Publication number: 20150249109Abstract: A method for manufacturing the image sensor device is provided. The method includes depositing a first dielectric layer over a back surface of a substrate, forming a ridge over the first dielectric layer, depositing a second dielectric layer over the first dielectric layer, including filling in a space between two adjacent ridges. The method also includes removing the ridge to form a trench in the second dielectric layer and forming a metal grid in the trench.Type: ApplicationFiled: March 3, 2014Publication date: September 3, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chien Wang, Chihy-Yuan Cheng, Chuan-Ling Wu, Chun-Chang Chen, Wang-Pen Mo, Feng-Jia Shiu
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Patent number: 8809179Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.Type: GrantFiled: March 9, 2007Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Wei Wang, Derek Lin, Chen-Ming Huang, Chang-Jen Hsieh, Chi-Hsin Lo, Chung-Yi Yu, Feng-Jia Shiu, Yeur-Luen Tu, Yi-Shin Chu, Jen-Sheng Yang
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Publication number: 20140185025Abstract: The present disclosure provides one embodiment of a lithography system for integrated circuit making. The system includes a substrate stage designed to secure a substrate and being operable to move the substrate; an alignment module that includes a tunable light source being operable to generate an infrared light with a wavelength tunable; and a detector to receive the light; and an exposing module integrated with the alignment module and designed to performing an exposing process to a resist layer coated on the substrate.Type: ApplicationFiled: January 2, 2013Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hsien Lin, Hung-Chang Hsieh, Feng-Jia Shiu, Chun-Yi Lee
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Publication number: 20130249041Abstract: The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy.Type: ApplicationFiled: May 10, 2013Publication date: September 26, 2013Inventors: Jen-Cheng Liu, Ching-Hung Cheng, Chien-Hsien Tseng, Chia-Hao Hsu, Feng-Jia Shiu, Shou-Gwo Wuu
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Patent number: 8466070Abstract: A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed.Type: GrantFiled: June 2, 2011Date of Patent: June 18, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsing-Fei Chou, Chia-Hua Chu, Jieh-Jang Chen, Feng-Jia Shiu, Hung Chang Hsieh
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Patent number: 8440495Abstract: The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy.Type: GrantFiled: March 6, 2007Date of Patent: May 14, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jen-Cheng Liu, Chin-Hong Cheng, Chien-Hsien Tseng, Alex Hsu, Feng-Jia Shiu, Shou-Gwo Wuu
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Patent number: 8409456Abstract: A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.Type: GrantFiled: April 20, 2011Date of Patent: April 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shun-Wei Lan, Jieh-Jang Chen, Shih-Wei Lin, Feng-Jia Shiu, Hung Chang Hsieh
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Patent number: 8357561Abstract: A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate having a front surface and a back surface; forming an alignment mark at the front surface of the substrate, wherein the alignment mark is detectable for alignment from the back surface; and processing the substrate from the back surface by performing registration from the back surface and using the alignment mark as a reference.Type: GrantFiled: March 9, 2011Date of Patent: January 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chi Fu, Gwo-Yuh Shiau, Liang-Lung Yao, Yuan-Chih Hsieh, Feng-Jia Shiu
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Publication number: 20120309197Abstract: A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed.Type: ApplicationFiled: June 2, 2011Publication date: December 6, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsing-Fei CHOU, Chia-Hua CHU, Jieh-Jang CHEN, Feng-Jia SHIU, Hung Chang HSIEH
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Publication number: 20120266810Abstract: A system for planarizing a semiconductor device includes a holder component for holding the substrate. The substrate has at least one opening therein, and each opening defines a lower portion and an upper portion. A resist applicator applies a layer of resist over the substrate, such that the resist layer covers the lower and upper portions. An etching component etches back the resist layer to expose the upper portion of the at least one opening. The resist applicator and the etching component repeat the steps of applying and etching, respectively, to remove a predetermined amount below the upper portion. A deposition component deposits an insulating layer over the substrate. A planarizing component planarizes the insulating layer until the upper portion of the at least one opening is exposed.Type: ApplicationFiled: July 18, 2011Publication date: October 25, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shun-Wei LAN, Jieh-Jang CHEN, Shih-Wei LIN, Feng-Jia SHIU, Hung Chang HSIEH
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Publication number: 20120270398Abstract: A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.Type: ApplicationFiled: April 20, 2011Publication date: October 25, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shun-Wei LAN, Jieh-Jang CHEN, Shih-Wei LIN, Feng-Jia SHIU, Hung Chang HSIEH
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Patent number: 8178422Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side and a back side, the device substrate having a first refractive index, forming an embedded target over the front side of the device substrate, forming a reflective layer over the embedded target, forming a media layer over the back side of the device substrate, the media layer having a second refractive index less than the first refractive index, and projecting radiation through the media layer and the device substrate from the back side so that the embedded target is detected for a semiconductor process.Type: GrantFiled: March 31, 2009Date of Patent: May 15, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alex Hsu, Shih-Chi Fu, Feng-Jia Shiu, Chia-Shiung Tsai
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Patent number: 8110881Abstract: A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit.Type: GrantFiled: September 27, 2007Date of Patent: February 7, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ya-Chen Kao, Chun-Jung Lin, Yu-Jen Wang, Hsu-Chen Cheng, Feng-Jia Shiu, Yung-Tao Lin
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Publication number: 20110159631Abstract: A method for fabricating a backside illuminated image sensor is provided. An exemplary method can include providing a substrate having a front surface and a back surface; forming an alignment mark at the front surface of the substrate, wherein the alignment mark is detectable for alignment from the back surface; and processing the substrate from the back surface by performing registration from the back surface and using the alignment mark as a reference.Type: ApplicationFiled: March 9, 2011Publication date: June 30, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chu Fu, Gwo-Yuh Shiau, Liang-Lung Yao, Yuan-Chih Hsieh, Feng-Jia Shiu