Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate and a vertical transistor. The vertical transistor is disposed on the substrate. The vertical transistor comprises an insulating layer, a source, a drain, a gate insulating layer and a gate. The source and the drain are arranged below and above the insulating layer, and the gate insulating layer surrounds the insulating layer, the source and the drain. The gate covers the gate insulating layer, and the gate insulating layer separates the gate from the source and separates the gate from the drain.

Abstract: A memory circuit includes a first memory cell array configured to store data, and a second memory cell array. The second memory cell array is configured as a first logic circuit or a second logic circuit in response to a first set of control signals. The first logic circuit is configured to perform a first logic function on a first set of data signals based on a second set of control signals. The second logic circuit is configured to perform a second logic function on the first set of data signals based on the second set of control signals. The second logic function is different from the first logic function. The first set of data signals is part of the data stored in the first memory cell array. The first memory cell array and the second memory cell array are embedded in a same memory cell array.

Abstract: A disclosed capacitor structure includes a support structure including a plurality of elongated structures each extending along a longitudinal direction, a transverse direction, and a vertical direction. The plurality of elongated structures includes an alternating stack of first dielectric layers and second dielectric layers, a bottom electrode formed over the support structure, a third dielectric layer formed over the bottom electrode, and a top electrode formed over the third dielectric layer. Each of the first dielectric layers includes a first width along the transverse direction and each of the second dielectric layers includes a second width along the transverse direction. In various embodiments, the first width may be less than the second width such that each of the plurality of elongated structures include walls including a corrugated width profile as a function of distance along the vertical direction. The capacitor structure may be formed in a BEOL process.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure.

Abstract: The present disclosure relates to an image sensor integrated chip (IC) structure. The image sensor IC structure includes a plurality of image sensing elements respectively disposed within a plurality of pixel regions of a pixel array within a substrate. An inter-level dielectric (ILD) structure is disposed on a surface of the substrate and surrounds one or more interconnects. A plurality of three-dimensional (3D) capacitors are arranged within respective ones of the plurality of pixel regions and are coupled to one of the plurality of image sensing elements by the one or more interconnects. The plurality of 3D capacitors include a base region extending in parallel to the surface of the substrate and one or more fingers extending outward from the base region along a direction perpendicular to the surface of the substrate.

Abstract: Some embodiments relate to an integrated device, including a first contact wire comprising an upper surface over a substrate; a plurality of shielding wires level with the first contact wire and having upper surfaces that are level with the upper surface of the first contact wire; and a first capacitor having an upper layer and a plurality of protrusions including a first protrusion and a second protrusion extending from the upper layer in a first direction towards the shielding wires; wherein the first protrusion extends to the upper surface of the first contact wire; and wherein the second protrusion is over and separated from the shielding wires in the first direction.

Abstract: A memory device having a capacitor structure and a method of forming the same are provided. The memory device includes a substrate; a dielectric layer disposed on the substrate; and a plurality of capacitor structures respectively disposed in the dielectric layer. Each capacitor structure includes: a cup-shaped lower electrode; a first upper electrode conformally covering an outer surface of the cup-shaped lower electrode; a first capacitor dielectric layer disposed between the outer surface of the cup-shaped lower electrode and the first upper electrode; a second upper electrode conformally covering an inner surface of the cup-shaped lower electrode, wherein the second upper electrode is electrically connected to the first upper electrode by at least one connection via; and a second capacitor dielectric layer disposed between the inner surface of the cup-shaped lower electrode and the second upper electrode.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device includes at least three metal plates that are spaced from one another. The MIM device further includes a plurality of capacitor insulator structures. Each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via (TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.

Abstract: A device structure includes a two-dimensional array of memory cells embedded in a memory-level dielectric layer and overlying a substrate; first access lines electrically connected to a respective row of memory cells within the two-dimensional array; and a first decoder circuit including first cantilever nanoelectromechanical devices that overlie the two-dimensional array of memory cells, are embedded in upper dielectric material layers, and have output nodes that are electrically connected to a respective first access line selected from the first access lines.

Abstract: In some embodiments, the present disclosure relates to method of forming an integrated circuit, including forming a semiconductor device on a frontside of a semiconductor substrate; depositing a dielectric layer over a backside of the semiconductor substrate; patterning the dielectric layer to form a first opening in the dielectric layer so that the first opening exposes a surface of the backside of the semiconductor substrate; depositing a glue layer having a first thickness over the first opening; filling the first opening with a first material to form a backside contact that is separated from the semiconductor substrate by the glue layer; and depositing more dielectric layers, bonding contacts, and bonding wire layers over the dielectric layer to form a second bonding structure on the backside of the semiconductor substrate, so that the backside contact is coupled to the bonding contacts and the bonding wire layers.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.

Abstract: An image sensor includes a substrate including a first surface and a second surface opposite to the first surface; a plurality of pixel sensors disposed in the substrate, a sensor isolation feature disposed in the substrate defining an active region, and a dielectric layer between the sensor isolation feature and the substrate, wherein the sensor isolation feature comprises a conductive material.

Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic module including a carrier structure, at least one first electronic element disposed on a first side of the carrier structure, at least one second electronic element disposed on a second side of the carrier structure, and a plurality of conductive elements is stacked on a substrate via the plurality of conductive elements and a substrate frame, so as to increase an accommodation space between the electronic module and the substrate, thereby preventing the at least one second electronic element of the electronic module from colliding with the substrate.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure.

Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.

Abstract: A semiconductor device includes a substrate having a front side and a back side opposite to each other. A plurality of photodetectors is disposed in the substrate within a pixel region. An isolation structure is disposed within the pixel region and between the photodetectors. The isolation structure includes a back side isolation structure extending from the back side of the substrate to a position in the substrate. A conductive plug structure is disposed in the substrate within a periphery region. A conductive cap is disposed on the back side of the substrate and extends from the pixel region to the periphery region and electrically connects the back side isolation structure to the conductive plug structure. A conductive contact lands on the conductive plug structure, and is electrically connected to the back side isolation structure through the conductive plug structure and the conductive cap.

Abstract: A memory device having a capacitor structure and a method of forming the same are provided. The memory device includes a substrate; a dielectric layer disposed on the substrate; and a plurality of capacitor structures respectively disposed in the dielectric layer. Each capacitor structure includes: a cup-shaped lower electrode; a first upper electrode conformally covering an outer surface of the cup-shaped lower electrode; a first capacitor dielectric layer disposed between the outer surface of the cup-shaped lower electrode and the first upper electrode; a second upper electrode conformally covering an inner surface of the cup-shaped lower electrode, wherein the second upper electrode is electrically connected to the first upper electrode by at least one connection via; and a second capacitor dielectric layer disposed between the inner surface of the cup-shaped lower electrode and the second upper electrode.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed on a first side of a substrate. A second via is disposed on the first side of the substrate and is laterally separated from the first via. An interconnect wire vertically contacts the second via. A through-substrate via (TSV) extends through the substrate to physically contact one or more of the second via and the interconnect wire. The first via has a first width and the second via has a second width. The second width is between approximately 2,000% and approximately 5,000% larger than the first width.