Patents by Inventor Feng Kuan
Feng Kuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11994713Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.Type: GrantFiled: March 20, 2023Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Chen, Hui Yu Lee, Jui-Feng Kuan, Chien-Te Wu
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Patent number: 11961769Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.Type: GrantFiled: November 7, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
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Publication number: 20240113237Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a sensing device, a solar cell, and an interconnecting structure. The solar cell is disposed above the sensing device and is electrically connected to the sensing device. The interconnecting structure is disposed between the sensing device and the solar cell and has a first surface facing the solar cell and a second surface facing the sensing devices. The interconnecting structure comprises a first energy storage component and a second energy storage component. The first energy storage component is disposed closer to the first surface of the interconnecting structure than the second energy storage component.Type: ApplicationFiled: January 10, 2023Publication date: April 4, 2024Inventors: FENG-CHIEN HSIEH, YUN-WEI CHENG, KUO-CHENG LEE, CHENG-MING WU, PING KUAN CHANG
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Publication number: 20240045322Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.Type: ApplicationFiled: October 20, 2023Publication date: February 8, 2024Inventors: YU-HAO CHEN, HUI-YU LEE, JUI-FENG KUAN, CHIEN-TE WU
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Patent number: 11852967Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.Type: GrantFiled: March 23, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Hao Chen, Hui-Yu Lee, Jui-Feng Kuan, Chien-Te Wu
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Publication number: 20230384538Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Yu-Hao CHEN, Hui-Yu Lee, Chung-Ming Weng, Jui-Feng Kuan, Chien-Te Wu
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Publication number: 20230389428Abstract: A method of manufacturing a semiconductor structure includes forming a first dielectric layer surrounding an optical component. The method further includes forming a thermal control mechanism adjacent to the optical component and at least partially surrounded by the first dielectric layer. Forming the thermal control mechanism includes forming a first thermoelectric member having a first conductivity type, forming a second thermoelectric member having a second conductivity type opposite to the first conductivity type, wherein the second thermoelectric member is opposite to the first thermoelectric member; and forming a conductive structure over and electrically connected to the thermal control mechanism. The method further includes forming a second dielectric layer over the first dielectric layer and surrounding the conductive structure.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Yu-Hao CHEN, Hui Yu LEE, Jui-Feng KUAN
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Publication number: 20230384537Abstract: A method of making a semiconductor device includes defining an opening extending from a first side of a substrate to a second side of the substrate, wherein the first side of the substrate is opposite the second side of the substrate. The method further includes depositing a dielectric material into the opening, wherein the dielectric material has a first refractive index. The method further includes etching the dielectric material to define a core opening extending from the first side of the substrate to the second side of the substrate. The method further includes depositing a core material into the core opening, wherein the core material has a second refractive index different from the first refractive index, and the core material is optically transparent. The method further includes removing excess core material from a surface of the substrate.Type: ApplicationFiled: July 25, 2023Publication date: November 30, 2023Inventors: Yu-Hao CHEN, Chung-Ming WENG, Tsung-Yuan YU, Hui Yu LEE, Hung-Yi KUO, Jui-Feng KUAN, Chien-Te WU
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Patent number: 11754794Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a waveguide on a first side of the substrate. The semiconductor device further includes a photodetector (PD) on a second side of the substrate, opposite the first side of the substrate. The semiconductor device further includes an optical through via (OTV) optically connecting the PD with the waveguide, wherein the OTV extends through the substrate from the first side of the substrate to the second side of the substrate.Type: GrantFiled: July 16, 2021Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Chen, Chung-Ming Weng, Tsung-Yuan Yu, Hui Yu Lee, Hung-Yi Kuo, Jui-Feng Kuan, Chien-Te Wu
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Patent number: 11740415Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.Type: GrantFiled: May 14, 2021Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao Chen, Hui-Yu Lee, Chung-Ming Weng, Jui-Feng Kuan, Chien-Te Wu
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Publication number: 20230228939Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.Type: ApplicationFiled: March 20, 2023Publication date: July 20, 2023Inventors: Yu-Hao Chen, Hui Yu Lee, Jui-Feng Kuan, Chien-Te Wu
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Patent number: 11609374Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.Type: GrantFiled: September 3, 2021Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Chen, Hui Yu Lee, Jui-Feng Kuan, Chien-Te Wu
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Publication number: 20230031333Abstract: An integrated circuit device includes a semiconductor substrate, an active area in a surface of the semiconductor substrate, a gate electrode, source and drain regions in the active area on opposite sides of the gate electrode to form a transistor, an active conductive pattern connected to a first plurality of electrical contacts for applying electrical signals to the transistor, and a dummy conductive pattern connected to a first plurality of thermal contacts for removing heat from the first active area, where the thermal contacts are electrically isolated from receiving the electrical signals applied to the electrical contacts.Type: ApplicationFiled: January 13, 2022Publication date: February 2, 2023Inventors: Yu-Hao CHEN, Hui Yu LEE, Jui-Feng KUAN, Chien-Te WU
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Patent number: 11532613Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.Type: GrantFiled: February 1, 2021Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hui-Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Yi-Kan Cheng
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Publication number: 20220381999Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a waveguide on a first side of the substrate. The semiconductor device further includes a photodetector (PD) on a second side of the substrate, opposite the first side of the substrate. The semiconductor device further includes an optical through via (OTV) optically connecting the PD with the waveguide, wherein the OTV extends through the substrate from the first side of the substrate to the second side of the substrate.Type: ApplicationFiled: July 16, 2021Publication date: December 1, 2022Inventors: Yu-Hao CHEN, Chung-Ming WENG, Tsung-Yuan YU, Hui Yu LEE, Hung-Yi KUO, Jui-Feng KUAN, Chien-Te WU
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Publication number: 20220365294Abstract: Disclosed are apparatus and methods for a silicon photonic (SiPh) structure comprising the integration of an electrical integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PIC and formed by layers of cladding polymer and core polymer; and an integration fan-out redistribution (InFO RDL) layer disposed on top of the two or more PWGs. The operation of PWGs is based on the refractive indexes of the cladding and core polymers. Inter-layer optical signals coupling is provided by edge-coupling, reflective prisms and grating coupling. A wafer-level system implements a SiPh structure die and provides inter-die signal optical interconnections among the PWGs.Type: ApplicationFiled: May 14, 2021Publication date: November 17, 2022Inventors: Yu-Hao CHEN, Hui-Yu LEE, Chung-Ming WENG, Jui-Feng KUAN, Chien-Te WU
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Publication number: 20220342238Abstract: A semiconductor structure includes, an optical component and a thermal control mechanism. The optical component includes a first main path that splits into a first side path and a second side path so that the first side path and the second side path are separated from one another. The thermal control mechanism configured to control a temperature of both the first side path and the second side path, wherein the first thermal control mechanism includes a first thermoelectric member and a second thermoelectric member that are positioned between the first side path and the second side path and the first thermoelectric member and the second thermoelectric member have opposite conductive types.Type: ApplicationFiled: July 27, 2021Publication date: October 27, 2022Inventors: Yu-Hao CHEN, Hui Yu LEE, Jui-Feng KUAN, Chien-Te WU
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Patent number: 11455453Abstract: A method includes assigning a default voltage value to a net in an integrated circuit (IC) schematic, generating a simulation voltage value of the net by performing a circuit simulation on the net using the assigned default voltage value, and modifying the IC schematic to include a voltage value associated with the net. The voltage value associated with the net and included in the modified IC schematic is based on a comparison between the assigned default voltage value and the simulation voltage value of the net.Type: GrantFiled: February 25, 2021Date of Patent: September 27, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Wen Chang, Jui-Feng Kuan
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Publication number: 20220299707Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.Type: ApplicationFiled: September 3, 2021Publication date: September 22, 2022Inventors: Yu-Hao Chen, Hui Yu Lee, Jui-Feng Kuan, Chien-Te Wu
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Publication number: 20220245319Abstract: A method is disclosed herein. The method includes: providing, by an electronic design automation (EDA), a trigger signal to an application programming interface (API); providing, by the API, first parameters associated with parameterized cells in a netlist of an integrated circuit (IC); adjusting, by the API, the first parameters to generate second parameters associated with the parameterized cells in the netlist of the IC; updating, by the API, the netlist of the IC according to the second parameters; and performing, by the EDA, a simulation according to the netlist.Type: ApplicationFiled: April 12, 2022Publication date: August 4, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsun-Yu YANG, Ren-Hong FU, Chin-Cheng KUO, Jui-Feng KUAN