Abstract: A power over Ethernet device is provided. The power over Ethernet device includes a first Ethernet connector, an Ethernet transformer circuit, and a detection circuit. The first Ethernet connector is coupled to a second Ethernet connector of a network device via an Ethernet cable and has a first reserve pin and a second reserve pin. The Ethernet transformer circuit is coupled to the first Ethernet connector to provide a supply voltage to the Ethernet cable to transfer the supply voltage to the network device. The detection circuit receives the supply voltage and is coupled to the Ethernet transformer circuit, the first reserve pin, and the second reserve pin to provide a reference voltage to the first reserve pin and receives an identification voltage from the second reserve pin to determine whether the network device is a powered device.

Abstract: A power over Ethernet device is provided. The power over Ethernet device includes a first Ethernet connector, an Ethernet transformer circuit, and a detection circuit. The first Ethernet connector is coupled to a second Ethernet connector of a network device via an Ethernet cable and has a first reserve pin and a second reserve pin. The Ethernet transformer circuit is coupled to the first Ethernet connector to provide a supply voltage to the Ethernet cable to transfer the supply voltage to the network device. The detection circuit receives the supply voltage and is coupled to the Ethernet transformer circuit, the first reserve pin, and the second reserve pin to provide a reference voltage to the first reserve pin and receives an identification voltage from the second reserve pin to determine whether the network device is a powered device.

Abstract: A method for forming a semiconductor device includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. A thickness of the first portion of the dielectric layer is adjusted by either reducing the thickness or depositing additional dielectric material. A capacitor top plate is formed over the first portion of the dielectric layer.

Abstract: A method for forming a semiconductor device includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. A thickness of the first portion of the dielectric layer is adjusted by either reducing the thickness or depositing additional dielectric material. A capacitor top plate is formed over the first portion of the dielectric layer.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.

Abstract: An embodiment is a semiconductor device comprising a contact pad over a substrate, wherein the contact pad is disposed over an integrated circuit on the substrate and a first passivation layer over the contact pad. A first via in the first passivation layer, wherein the first via has more than four sides, and wherein the first via extends to the contact pad.

Abstract: A semiconductor device. The device includes an active region isolated by an isolation structure on a substrate, and a dielectric layer overlying the active region and the isolation structure. The dielectric layer comprises a lower part overlying the active region beyond the boundary of the active region and the isolation structure, and a protruding part overlying the boundary of the active region and the isolation structure.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.

Abstract: A semiconductor device. The device includes an active region isolated by an isolation structure on a substrate, and a dielectric layer overlying the active region and the isolation structure. The dielectric layer comprises a lower part overlying the active region beyond the boundary of the active region and the isolation structure, and a protruding part overlying the boundary of the active region and the isolation structure.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.

Abstract: A method of manufacturing a microelectronic device, including performing a first inspection of a device feature during an intermediate stage of manufacture, cleaning the device feature after the first inspection, and performing a second inspection of the device feature after cleaning the device feature.

Abstract: A method of manufacturing a microelectronic device, including performing a first inspection of a device feature during an intermediate stage of manufacture, cleaning the device feature after the first inspection, and performing a second inspection of the device feature after cleaning the device feature.

Abstract: Single spot laser focusing systems are widely used by photolithographic stepping systems. The stage is moved until a spot, located in the immediate area in which the image is to be projected, achieves minimum size. This system is sensitive to the local topography within the area of the image and this can lead to less than optimum results. The present invention overcomes this problem by a process in which the spot is always directed to fall within an alignment mark field (as opposed to within the integrated circuit field). Several ways for accomplishing this are described.