Abstract: A powertrain system includes a conversion device, a first motor, a second motor, and an engine. At least one of the first motor and the engine is configured to selectively output power to a first traveling end by means of the conversion device; the engine is configured to selectively output the power to the first motor by means of the conversion device, to drive the first motor to generate electricity; and the second motor is in driving connection with the engine, so that the powertrain system has a first simultaneous driving and electricity-generating mode. In the first simultaneous driving and electricity-generating mode, the first motor outputs the power to the first traveling end by means of the conversion device; and the second motor, driven by the engine, generates electricity.

Abstract: A chip storing device includes a supporting frame, an elastic airbag and an airtight container. The supporting frame includes a loading tray having a receiving slot and a positioning portion. The receiving slot is used for containing a packaged chip. The positioning portion is disposed within the receiving slot, and used for limiting the elastic airbag. The airtight container is formed with an accommodating space therein. The supporting frame and the elastic air bag are completely received within the accommodation space. when the accommodation space is evacuated to be in a negative pressure environment, the volume of the elastic airbag is increased in the negative pressure environment, so that the elastic airbag that is inflated directly abuts against the packaged chip within the receiving slot.

Abstract: An element pickup mechanism includes a pick-up arm and an elastic gasket. The pick-up arm includes a bracket, an air-extraction pipe and a suction cup. The bracket is provided with an inner space and an opening that is formed on one side of the bracket and in communication with the inner space. The air-extraction pipe is disposed on the bracket and connected to a vacuum pump equipment. The suction cup is sleeved on one end of the air-extraction pipe, located in the inner space and faced towards the opening of the bracket. The elastic gasket includes a flexible pad and a through hole. The flexible pad is formed with a flat surface and an attached surface that is fixedly attached to the side of the bracket. The through hole penetrates through the flexible pad to coaxially align with the opening and the suction cup.

Abstract: The present disclosure provides a storage control method, including: sending a command acquisition request for at least one first queue, where the at least one first queue is a queue among a plurality of queues which accumulates at least one queue request message, and a command acquisition request for each first queue of the at least one first queue corresponds to all accumulated queue request messages of the first queue; and receiving a storage command for each first queue in the at least one first queue.

Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.

Abstract: A display device includes a substrate, a photosensitive element formed above the substrate, a signal line formed above the substrate, and a transparent conductive member electrically connected to the signal line and the photosensitive element. In a normal direction of the substrate, the signal line does not overlap with the photosensitive element.

Abstract: A display device includes a backlight module and a display panel. The display panel is disposed on the backlight module and includes two substrates, a sensor, and a light-shielding element. The sensor is disposed between the two substrates. The light-shielding element at least partially surrounds the sensor. A height of the light-shielding element is greater than a height of the sensor.

Abstract: A planarization tool is configured to monitor and analyze the condition of a polishing pad over the life of the polishing pad. A piezoelectric pad monitoring device may be mounted to a polishing head of the planarization tool in place of a semiconductor wafer. The piezoelectric pad monitoring device may be pressed against the polishing pad. When pressed against the polishing pad, the piezoelectric pad monitoring device may generate a signal based on a quantity of pad contacts, on the polishing pad, that are in contact with the piezoelectric pad monitoring device. The signal may be provided to a processor of the planarization tool so that the processor may generate, based on the signal, a map of the pad contacts on the polishing pad. The processor may use the map of the pad contacts to determine properties of the polishing pad such as roughness and/or uniformity, among other examples.

Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.

Abstract: The semiconductor device includes a substrate, a stack disposed on the substrate, a first common source line and a second common source line disposed in the stack and connected to the substrate. The stack includes insulating layers and conductive layers alternately arranged. The first common source line and the second common source line are extended along a first direction and are arranged in a second direction that is perpendicular to the first direction. The first common source line includes a first segment and a second segment spaced apart by a first common source line cut. The second common source line includes a third segment and a fourth segment spaced apart by a second common source line cut. The first common source line cut is shifted relative to the second common source line cut in the first direction. A method of forming the semiconductor device is also disclosed.

Abstract: According to the embodiments provided herein, a photovoltaic device can include a buffer layer adjacent to an absorber layer doped p-type with a group V dopant. The buffer layer can have a plurality of layers compatible with group V dopants.

Abstract: The present disclosure provides an electronic device including a first sensing unit, a first transistor coupled to the first sensing unit, a second transistor coupled to the first transistor, a second sensing unit, a third transistor coupled to the second sensing unit, a fourth transistor coupled to the third transistor, a first signal line coupled to the second transistor and the fourth transistor, and a power line coupled to the first transistor and the third transistor, in which the power line is disposed between the first sensing unit and the second sensing unit.

Abstract: A semiconductor structure is provided. The semiconductor structure has a device region and a periphery region adjacent to the device region. The periphery region comprises an array contact defining region and a periphery contact defining region. The semiconductor structure comprises a substrate, a staircase structure, an etch stop layer, a plurality of array contacts, and a plurality of periphery contacts. The staircase structure is disposed on the substrate in the periphery region. The staircase structure comprises conductive layers and dielectric layers disposed alternately. The etch stop layer is disposed on the staircase structure in the array contact defining region. The array contacts are disposed on the staircase structure and through the etch stop layer in the array contact defining region. The periphery contacts are through the staircase structure in the periphery contact defining region.

Abstract: An ESD protection device includes a substrate, an epitaxial layer, first to third well regions, and first to sixth doped regions. The first to third well regions are disposed in the epitaxial layer. The third well region is disposed between the first and second well regions. The first and second doped regions are disposed on the first well region and coupled to a pad. The third and fourth doped regions are disposed on the second well region and coupled to a ground terminal. The fifth doped region is disposed on the third well region, and the sixth doped region is disposed in the fifth doped region. The third, fifth, and sixth doped regions have the same conductive type. In response to an electrostatic discharge event occurring on the pad, a discharge path is formed between the pad and the ground terminal.

Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies, and a benchmark circuit disposed on the scribe line. The benchmark circuit includes a first switching circuit, a first process control monitoring (PCM) device and a second PCM device coupled to the first switching circuit, and a second switching circuit. The first switching circuit is configured to selectively couple the first PCM device and the second PCM device to receive a test signal, wherein the first PCM device and the second PCM device are configured to output a first output signal and a second output signal in response to the test signal, respectively. The second switching circuit is configured to selectively couple the first PCM device and the second PCM device to output the first output signal or the second output signal.

Abstract: A testing device for testing an integrated circuit package is provided, including a printed circuit board, a testing socket, a conductive fastener, a cover, and a conductive element assembly. The printed circuit board includes a first metal layer formed on the bottom surface thereof. The testing socket is disposed above the printed circuit board. The conductive fastener is configured to secure the testing socket to the printed circuit board, wherein the conductive fastener is electrically connected to the first metal layer and the testing socket. The cover is disposed above the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket, wherein the cover makes electrical contact with the integrated circuit package. The conductive element assembly is disposed between and electrically connected to the cover and the testing socket.

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Abstract: An electrical connector includes an insulating housing, a plurality of first terminals, a plurality of second terminals, a metal element and a fastening assembly. The insulating housing has a first insulating body, a second insulating body surrounding the first insulating body, a third insulating body and a fourth insulating body. The third insulating body is disposed to a rear end of a top surface of the first insulating body. The fourth insulating body is disposed to a top surface of the third insulating body. The plurality of the first terminals are surrounded by the first insulating body and the second insulating body. The plurality of the second terminals are surrounded by the third insulating body. The metal element is disposed to an outer surface of the insulating housing. The fastening assembly is positioned above the fourth insulating body.

Abstract: The present disclosure provides an electronic device including a first sensing circuit, a second sensing circuit and a power line. The first sensing circuit includes a first sensing unit and a first transistor, and a first end of the first sensing unit is coupled to a control end of the first transistor. The second sensing circuit includes a second sensing unit and a second transistor, and a first end of the second sensing unit is coupled to a control end of the second transistor. A first end of the first transistor and a first end of the second transistor are coupled to the power line.

Abstract: The technology of this application relates to a frontlight module and a display apparatus. The frontlight module is disposed on a side of a display panel. The frontlight module includes a light source, a light guide plate, and light guide dots. The light guide plate includes a first surface and a second surface that are disposed opposite to each other. The display panel is disposed facing the second surface. The light source is disposed on a side surface of the light guide plate. A plurality of light guide dots are disposed on the first surface or the second surface of the light guide plate. Each light guide dot has a light guide surface disposed at an angle with respect to a surface of the light guide plate. Light is fully reflected and/or refracted on the light guide surfaces to propagate to the display panel.