Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

Abstract: A method for determining a loading current of a circuit board is provided. In the method, outline positions of metal regions and hollowed regions in each of the metal regions are recorded. Metal widths corresponding to scan lines in circuit board are calculated in a sequence, so that a minimum metal width on each of the scan lines is acquired. According to the minimum metal width, a maximum loading current of each of the metal regions is calculated. In addition, a method and a system for filtering manufacturers are provided. A processing apparatus of the system analyzes the maximum loading current and manufacturing process parameters of the circuit board, calculates a weight score of a manufacturing process capability parameter table of each manufacturer according to the maximum loading current and manufacturing process parameters, and filtering the manufacturers to produce the best fit manufacturer list.

Abstract: A method for determining a loading current of a circuit board is provided. In the method, outline positions of metal regions and hollowed regions in each of the metal regions are recorded. Metal widths corresponding to scan lines in circuit board are calculated in a sequence, so that a minimum metal width on each of the scan lines is acquired. According to the minimum metal width, a maximum loading current of each of the metal regions is calculated. In addition, a method and a system for filtering manufacturers are provided. A processing apparatus of the system analyzes the maximum loading current and manufacturing process parameters of the circuit board, calculates a weight score of a manufacturing process capability parameter table of each manufacturer according to the maximum loading current and manufacturing process parameters, and filtering the manufacturers to produce the best fit manufacturer list.

Abstract: A method for determining a loading current of a circuit board is provided. In the method, outline positions of metal regions and hollowed regions in each of the metal regions are recorded. Metal widths corresponding to scan lines in circuit board are calculated in a sequence, so that a minimum metal width on each of the scan lines is acquired. According to the minimum metal width, a maximum loading current of each of the metal regions is calculated. In addition, a method and a system for filtering manufacturers are provided. A processing apparatus of the system analyzes the maximum loading current and manufacturing process parameters of the circuit board, calculates a weight score of a manufacturing process capability parameter table of each manufacturer according to the maximum loading current and manufacturing process parameters, and filtering the manufacturers to produce the best fit manufacturer list.

Abstract: The invention relates to a driving circuit comprising a first bridge circuit, a second bridge circuit, a first protection device and a second protection device. The first bridge circuit comprising a first positive input terminal, a first negative input terminal, a first positive output terminal and a first negative output terminal is coupled to an AC voltage source to output a first voltage. The second bridge circuit comprising a second positive input terminal, a second negative input terminal, a second positive output terminal and a second negative output terminal is coupled to the AC voltage source to output a second voltage. The second and the first negative output terminals are both coupled to the ground potential. The first protection device is coupled between the second positive input terminal and the AC voltage source. The second protection device is coupled between the second negative input terminal and the AC voltage source.

Abstract: A temperature and illumination adjusting system, including: a temperature and illumination adjusting device, including a CPU, receiving a temperature value and an illumination value, and generating a first PWM value and a second PWM value according to a first formula and a second formula; and a communication unit, outputting the first PWM value and the second PWM value; and a lamp device, including a lamp communication unit, receiving the first PWM value and the second PWM value; a first light module; a second light module; a first PWM driving unit, driving the first light module with the first PWM value; a second PWM driving unit, driving the second light module with the second PWM value, wherein the outputs of the first light module and the second light module have different color temperature.

Abstract: An embodiment of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; generating a layout suggestion when the crosstalk value is larger than the predetermined value.

Abstract: A method for determining a loading current of a circuit board is provided. In the method, outline positions of metal regions and hollowed regions in each of the metal regions are recorded. Metal widths corresponding to scan lines in circuit board are calculated in a sequence, so that a minimum metal width on each of the scan lines is acquired. According to the minimum metal width, a maximum loading current of each of the metal regions is calculated. In addition, a method and a system for filtering manufacturers are provided. A processing apparatus of the system analyzes the maximum loading current and manufacturing process parameters of the circuit board, calculates a weight score of a manufacturing process capability parameter table of each manufacturer according to the maximum loading current and manufacturing process parameters, and filtering the manufacturers to produce the best fit manufacturer list.

Abstract: A dimmer circuit and a lighting apparatus using the same are provided. The dimmer circuit comprises a dimmer, a rectifier, a sample-and-hold unit, an integral unit and a current holding circuit. The dimmer is coupled to an AC for modulating the AC into an alternating signal. The rectifier couples the dimmer and the AC for rectifying the alternating signal into a DC signal. The sample-and-hold unit is coupled to the rectifier for sampling the DC signal to obtain an average positive wave pulse. The integral unit is coupled to the sample-and-hold unit for integrating the average positive wave pulse to generate a DC voltage. The current holding circuit comprises a switch and a bleeder. The current holding circuit determines the on/off state of the switch according to a comparison between the DC voltage and a reference voltage, such that the DC signal passes through the bleeder or the switch.

Abstract: The control method comprises the following steps. Firstly, whether a touch event occurs in a control device is determined. Then, responding to a color temperature set and a brightness set from the control device, a first PWM and a second PWM is generated. Then, whether the lamp connects with to the control device is determined. Then, the first PWM and the second PWM is packaged in a color control package if the lamp connects with to the control device. Then, the color control package is transmitted to the lamp in wireless.

Abstract: A dual-use light fixture having AC and DC LEDs includes a heat-dissipating housing, a printed circuit board located on a first end of the heat-dissipating housing, AC and DC LED chips located on the printed circuit board, and a power supply pedestal coupled to a second end of the heat-dissipating housing. The power supply pedestal includes an AC plug, a DC driving unit, and a thread connector. The AC plug is electrically connected to the printed circuit board for inserting into an AC outlet to provide an AC power. The DC driving unit is located in an accommodating space formed by the power supply pedestal and the heat-dissipating housing and is electrically connected to the printed circuit board. The thread connector is coupled to another AC power, and the AC power is converted into a DC power by the DC driving unit.

Abstract: A circuit-design method for a PCB is provided. A first user input is obtained via a user interface of a layout tool, wherein the first user input indicates that an object of a circuit diagram of the PCB is selected in the user interface. A plurality of constraint settings corresponding to an attribute are obtained from a database according to the attribute of the object. The plurality of constraint settings are displayed in a window of the user interface. A second user input is obtained via the user interface, wherein the second user input indicates that one of the plurality of constraint settings is selected in the window. At least one constraint parameter corresponding to the selected constraint setting is assigned to the object, and a tag corresponding to the attribute of the object is attached to the object of the circuit diagram.

Abstract: One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing a layout suggestion table when the crosstalk value is larger than the predetermined value.

Abstract: An embodiment of the disclosure provides a crosstalk analysis method executed by a computer including: executing a layout program for a layout circuit; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing an interface for showing information of the layout result and adjusting a plurality of lines of the layout circuit.

Abstract: An embodiment of the invention introduces a method for generating schematic diagrams, executed by a processing unit of an apparatus, which comprises the following steps. A pin-editing interface comprising a data table is generated to assist a user to configure pin settings. A user setting is obtained via the pin-editing interface, and a schematic diagram is generated on a display unit according to the obtained user setting.

Abstract: An embodiment of the invention introduces a method for generating schematic diagrams, executed by a processing unit of an apparatus, which comprises the following steps. A pin-editing interface comprising a data table is generated to assist a user to configure pin settings. A user setting is obtained via the pin-editing interface, and a schematic diagram is generated on a display unit according to the obtained user setting.

Abstract: An embodiment of the invention provides a lamp comprising a first emitting device, a second emitting device, and a control signal generation device. The control signal generation device generates a first control signal and a second control signal to control the first emitting device and the second emitting device, so that a first light flux generated by the first emitting device is equivalent to a second light flux generated by the second emitting device, wherein the second control signal is generated according to the first control signal.

Abstract: An embodiment of the invention provides a lamp comprising a control circuit and a light emitting device. The light emitting device comprises a plurality of light emitting units with different wavelengths. The control circuit calibrates a control signal according to an environment light to adjust a light spectrum of the light emitting device by controlling the luminance of each light emitting unit.

Abstract: An embodiment of the disclosure provides a crosstalk analysis method executed by a computer including: executing a layout program for a layout circuit; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing an interface for showing information of the layout result and adjusting a plurality of lines of the layout circuit.