Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Abstract: A method is provided for encoding K>1 sequentially presented video pictures. Each of the K pictures is divided into an m>1 row×n>1 column array of non-overlapping coding units of equal sizes. Each coding unit occupies a respective coding unit position in the picture from which it was divided. An arbitrary, pseudo random pattern of coding units is selected for refreshing during each of the K pictures. Each pattern selected during any given one of the K pictures includes a sequence of one or more coding units of the array. In addition, the pixels of each coding unit selected for refreshing during a kth picture occupy different pixel positions than each coding unit selected for refreshing during a preceding one of the 1st to (k?1)th pictures of the K pictures. Furthermore, each pixel position of a moving picture image formed from the K pictures is selected for refreshing once over the sequence of K pictures.

Abstract: An encoder system includes an internal counter (PTS or presentation time stamp counter). The counter provides information which enables the encoder system to resynchronize itself in the event synchronization with the video input stream is lost. Preferably, the counter is implemented in software. The encoder system also include a comparator (preferably implemented in software). The comparator is able to determine if particular regions of the input video stream have been captured at an expected time according to the internal counter within a predetermined error window by comparing the actual capture time with the expected capture time. In general, if the encoder system is synchronized with the incoming video stream, each successive blanking or active region will be captured at its expected time according to the internal counter within a predetermined error window. In this event, the timing of the various modules of the encoder system (e.g., preprocessing, spatial encoding, etc.

Abstract: In accordance with the invention, a method, for coding multi-mode predictive interpolative coded fields of video, includes the steps of:(a) providing a current field of interlaced pixel data, and past and future fields of such data;(b) providing estimated pixel data at omitted line positions in the past and future fields of data to form enhanced fields of pixel data;(c) comparing a block of pixel data from the current field with corresponding blocks of data from such past and future fields to derive motion vector signals indicative of best matched blocks of data;(d) developing pixel error signals representing pixel by pixel errors based on utilization of best matched blocks in different modes for comparison with the block of pixel data from the current field and developing best mode signals indicative of which of such modes represents the least overall error; and(e) providing the best mode signals, motion vector signals, pixel error signals, and the future odd field of data for transmission for use by a decod

Abstract: Deinterlacing systems and methods useful with television and other interlaced data signals derive values for pixels on missing lines using best matching values for blocks of pixels through time-recursive comparison of current pixels block values with such values for prior frames of data and also with later frames. Noise propagation is attenuated by mixing of current interpolated pixel data and memory size efficiency is achieved by comparisons based on blocks of pixels, with the block size adjustable for data accuracy. Use of chrominance signal comparisons and reduced data rate coding techniques provide added capabilities to the deinterlacing systems and methods.