Abstract: Examples of the present disclosure provide a memory system and a method thereof, and a system. The memory system comprises a memory device and a memory controller coupled to the memory device, wherein the memory controller comprises a PCIe interface, and the memory controller is further configured to: generate a first data packet message encapsulated in a PCIe protocol format, wherein a data packet of the first data packet message is encapsulated with at least a portion of a first data unit, and the first data unit is generated in another protocol format different from the PCIe protocol format; and send the first data packet message through the PCIe interface.

Abstract: According to one aspect of the present disclosure, a method of operating a memory system is provided. The method may include receiving a first command sent by a first user. The memory system may be configured with a first namespace accessible by the first user and a second namespace accessible by a second user, and the first command may carry an identifier corresponding to file set information of the second namespace. The method may include copying data corresponding to the file set information in the second namespace to the first namespace based on the identifier in response to the first command.

Abstract: A test equipment includes a selection register configured to store a selection index determined based on a selection command, a first tester channel including a first waveform driving device, and a second tester channel including a second waveform driving device. Each of the first tester channel and the second tester channel is multiplexed by a plurality of Device Under Test (DUTs). The first waveform driving device and the second waveform driving device are coupled to the selection register. The first waveform driving device is configured to generate, based on a driving source signal, a first waveform signal for driving multiple of first pins of the plurality of DUTs, and control, based on the selection index and a first bit map corresponding to the first tester channel, an output of the first waveform signal through the first tester channel.

Abstract: In certain aspects, a pattern generation system includes a memory and a processor coupled to the memory. The memory is configured to store a lookup table set. The lookup table set includes a mapping relationship between source patterns and a set of test channels, and is indexed based on a pin function index. The processor is configured to generate the source patterns, execute a pin-mapping operation based on an instruction to obtain a set of source selection signals for the set of test channels based on the pin function index and the lookup table set, and select and output a source signal from the source patterns for each test channel based on a corresponding source selection signal for the respective test channel.

Abstract: A test equipment includes a selection register configured to store a selection index determined based on a selection command, a first tester channel including a first waveform driving device, and a second tester channel including a second waveform driving device. Each of the first tester channel and the second tester channel is multiplexed by a plurality of Device Under Test (DUTs). The first waveform driving device and the second waveform driving device are coupled to the selection register. The first waveform driving device is configured to generate, based on a driving source signal, a first waveform signal for driving multiple of first pins of the plurality of DUTs, and control, based on the selection index and a first bit map corresponding to the first tester channel, an output of the first waveform signal through the first tester channel.

Abstract: In certain aspects, a waveform driving device for a tester channel includes a waveform generator, a bit map register, and an output logic circuit. The waveform generator is configured to generate a waveform signal based on a driving source signal. The bit map register is configured to store a bit map associated with the tester channel. The output logic circuit is coupled to the bit map register and the waveform generator, and configured to control an output of the waveform signal through the tester channel based on a bit control signal from the bit map.

Abstract: In certain aspects, a pattern generation system includes a memory and a processor coupled to the memory. The memory is configured to store a lookup table set. The lookup table set includes a mapping relationship between source patterns and a set of test channels, and is indexed based on a pin function index. The processor is configured to generate the source patterns, execute a pin-mapping operation based on an instruction to obtain a set of source selection signals for the set of test channels based on the pin function index and the lookup table set, and select and output a source signal from the source patterns for each test channel based on a corresponding source selection signal for the respective test channel.

Abstract: In certain aspects, a pattern generation system includes a pattern generator, a memory, a pin function register, a pin function mapper, and a set of source selectors. The pattern generator generates a plurality of source patterns. The memory stores a lookup table set. The lookup table set describes a mapping relationship between the plurality of source patterns and a set of test channels, and is indexed based on a pin function index. The pin function register stores a value of the pin function index. The pin function mapper executes a pin-mapping operation to generate a set of source selection signals based on the value of the pin function index and the lookup table set. Each source selector selects and outputs a source signal from the plurality of source patterns to a corresponding test channel based on a corresponding source selection signal received from the pin function mapper.

Abstract: In certain aspects, a waveform driving device for a tester channel includes a waveform generator, a bit map register, and an output logic circuit. The waveform generator is configured to generate a waveform signal based on a driving source signal. The bit map register is configured to store a bit map associated with the tester channel. The output logic circuit is coupled to the bit map register and the waveform generator, and configured to control an output of the waveform signal through the tester channel based on a bit control signal from the bit map.

Abstract: In certain aspects, a pattern generation system includes a pattern generator, a memory, a pin function register, a pin function mapper, and a set of source selectors. The pattern generator generates a plurality of source patterns. The memory stores a lookup table set. The lookup table set describes a mapping relationship between the plurality of source patterns and a set of test channels, and is indexed based on a pin function index. The pin function register stores a value of the pin function index. The pin function mapper executes a pin-mapping operation to generate a set of source selection signals based on the value of the pin function index and the lookup table set. Each source selector selects and outputs a source signal from the plurality of source patterns to a corresponding test channel based on a corresponding source selection signal received from the pin function mapper.