Abstract: A test equipment includes a selection register configured to store a selection index determined based on a selection command, a first tester channel including a first waveform driving device, and a second tester channel including a second waveform driving device. Each of the first tester channel and the second tester channel is multiplexed by a plurality of Device Under Test (DUTs). The first waveform driving device and the second waveform driving device are coupled to the selection register. The first waveform driving device is configured to generate, based on a driving source signal, a first waveform signal for driving multiple of first pins of the plurality of DUTs, and control, based on the selection index and a first bit map corresponding to the first tester channel, an output of the first waveform signal through the first tester channel.

Abstract: In certain aspects, a waveform driving device for a tester channel includes a waveform generator, a bit map register, and an output logic circuit. The waveform generator is configured to generate a waveform signal based on a driving source signal. The bit map register is configured to store a bit map associated with the tester channel. The output logic circuit is coupled to the bit map register and the waveform generator, and configured to control an output of the waveform signal through the tester channel based on a bit control signal from the bit map.

Abstract: In certain aspects, a pattern generation system includes a memory and a processor coupled to the memory. The memory is configured to store a lookup table set. The lookup table set includes a mapping relationship between source patterns and a set of test channels, and is indexed based on a pin function index. The processor is configured to generate the source patterns, execute a pin-mapping operation based on an instruction to obtain a set of source selection signals for the set of test channels based on the pin function index and the lookup table set, and select and output a source signal from the source patterns for each test channel based on a corresponding source selection signal for the respective test channel.

Abstract: In certain aspects, a pattern generation system includes a pattern generator, a memory, a pin function register, a pin function mapper, and a set of source selectors. The pattern generator generates a plurality of source patterns. The memory stores a lookup table set. The lookup table set describes a mapping relationship between the plurality of source patterns and a set of test channels, and is indexed based on a pin function index. The pin function register stores a value of the pin function index. The pin function mapper executes a pin-mapping operation to generate a set of source selection signals based on the value of the pin function index and the lookup table set. Each source selector selects and outputs a source signal from the plurality of source patterns to a corresponding test channel based on a corresponding source selection signal received from the pin function mapper.

Abstract: In certain aspects, a waveform driving device for a tester channel includes a waveform generator, a bit map register, and an output logic circuit. The waveform generator is configured to generate a waveform signal based on a driving source signal. The bit map register is configured to store a bit map associated with the tester channel. The output logic circuit is coupled to the bit map register and the waveform generator, and configured to control an output of the waveform signal through the tester channel based on a bit control signal from the bit map.

Abstract: In certain aspects, a pattern generation system includes a pattern generator, a memory, a pin function register, a pin function mapper, and a set of source selectors. The pattern generator generates a plurality of source patterns. The memory stores a lookup table set. The lookup table set describes a mapping relationship between the plurality of source patterns and a set of test channels, and is indexed based on a pin function index. The pin function register stores a value of the pin function index. The pin function mapper executes a pin-mapping operation to generate a set of source selection signals based on the value of the pin function index and the lookup table set. Each source selector selects and outputs a source signal from the plurality of source patterns to a corresponding test channel based on a corresponding source selection signal received from the pin function mapper.

Abstract: A method for plasma etching a wafer after a backside grinding process which incorporates an oxidation pretreatment step is disclosed. The method includes the step of first grinding a backside of a wafer to expose a bare silicon surface. The bare silicon surface is then oxidized in an oxidation chamber to form a substantially uniform silicon oxide layer of at least 50 ? thick, and preferably at least 100 ? thick. The wafer is then positioned in a plasma etch chamber with an active surface of the wafer exposed, and a surface layer etched away by an oxygen plasma without causing any further silicon oxide formation on the backside of the wafer. The present invention novel plasma etching method can be advantageously used for removing an organic material layer, such as a photoresist layer from a wafer surface.

Abstract: A method for plasma etching a wafer after a backside grinding process which incorporates an oxidation pretreatment step is disclosed. The method includes the step of first grinding a backside of a wafer to expose a bare silicon surface. The bare silicon surface is then oxidized in an oxidation chamber to form a substantially uniform silicon oxide layer of at least 50 Å thick, and preferably at least 100 Å thick. The wafer is then positioned in a plasma etch chamber with an active surface of the wafer exposed, and a surface layer etched away by an oxygen plasma without causing any further silicon oxide formation on the backside of the wafer. The present invention novel plasma etching method can be advantageously used for removing an organic material layer, such as a photoresist layer from a wafer surface.

Abstract: A microelectronic device including a substrate having a top metal layer, a first passivation layer overlying the substrate and wherein the passivation layer includes a via defined at least in part by a side wall of the passivation layer, and wherein the via overlies the top metal layer, a dielectric spacer positioned the via and the spacer having and inner wall with arcuate shape, an the electrically conductive redistribution layer having a portion positioned overlying the inner wall of the spacer and wherein the redistribution layer includes a portion in electrical contact with the top metal layer.