Abstract: A system and method for optimizing data routing in a reconfigurable processor by differentiating between primary vector-based ports and secondary staging ports of compute units. The method includes receiving a placement graph defining unplaced memory units, compute units, and data connections classified as primary connections through vector-based streaming ports or secondary connections through staging ports. The system forms computational clusters by grouping memory units with compute units connected via primary ports, assigns these clusters to a reconfigurable computing grid according to port topology, and routes data paths by prioritizing low-latency primary port connections while utilizing secondary ports for data staging. A configuration file is generated that optimizes data flow through the differentiated port architecture, enabling efficient execution of parallel computation tasks such as matrix operations and neural network processing.

Abstract: A method for optimizing the placement and routing of compute units and memory units within a reconfigurable computing grid is disclosed. The method involves obtaining a hardware description of the computing grid, receiving a placement graph for a computing task, forming subgraphs for unplaced memory units with primary connections, assigning subgraphs as clusters on the grid, and generating a configuration file for a physical reconfigurable processor. By strategically placing clusters on the grid and configuring the processor based on the logical representation, efficient execution of reconfigurable computing tasks is achieved. This method enhances the performance and flexibility of reconfigurable computing systems by streamlining the allocation of compute and memory resources.

Abstract: A method for reducing latency and increasing throughput in a reconfigurable computing system includes receiving a user program for execution on a reconfigurable dataflow computing system, comprising a grid of interconnected compute units and grid of memory units. The user program includes multiple tensor-based algebraic expressions that are converted to an intermediate representation comprising multiple stages. Each stage includes one or more logical operations executable via dataflow through compute units, and each stage is preceded by and followed by a stage buffer, each stage buffer corresponding to one or more memory units. The method includes detecting a final joining stage that consumes a first and second dataflow path, having a first and second total stage buffer depth, respectively, and balancing the first and second total stage buffer depths via tuning or inserting a whole stage buffer, wherein a total associated PMU cost is minimized.

Abstract: Systems and methods are disclosed for transforming a high-level program of a computing task into configuration data executable by a reconfigurable dataflow processor (RDP) including one or more arrays of configurable units where the compiler may include a first, second and third compiler levels. The third compiler level may receive a first intermediate representation (IR) of the high-level program generated by the second compiler level where the first IR is based on a second IR generated by the first compiler level. The third compiler level may determine a failure occurred during generating of the configuration data based on the first IR, determine, based on the failure and error handling data for the failure, whether to return compilation operations to one of the first compiler level or the second compiler level and return the compilation operations to the determined one of the first compiler level and the second compiler level.

Abstract: A method for optimizing the placement and routing of compute units and memory units within a reconfigurable computing grid is disclosed. The method involves obtaining a hardware description of the computing grid, receiving a placement graph for a computing task, forming subgraphs for unplaced memory units with primary connections, assigning subgraphs as clusters on the grid, and generating a configuration file for a physical reconfigurable processor. By strategically placing clusters on the grid and configuring the processor based on the logical representation, efficient execution of reconfigurable computing tasks is achieved. This method enhances the performance and flexibility of reconfigurable computing systems by streamlining the allocation of compute and memory resources.

Abstract: A method for placing, routing and using compute units and memory units in a reconfigurable computing grid includes receiving a placement graph for a computing task that defines a set of unplaced memory units, a set of unplaced compute units and data connections between the unplaced memory units and the unplaced compute units, the data connections comprising primary connections corresponding to the primary ports of the unplaced compute units and secondary connections corresponding to the secondary ports of the unplaced compute units. The method also includes forming a subgraph for each unplaced memory unit having a primary connection, each subgraph comprising the unplaced memory unit and each unplaced compute unit connected to the unplaced memory unit via a primary connection. The method also includes placing each formed subgraph as a cluster on the reconfigurable computing grid. A corresponding computer program product and system are also disclosed herein.

Abstract: Provided is a single-polarized antenna. This single-polarized antenna includes a power divider and a Vivaldi oscillator array. The Vivaldi oscillator array includes multiple Vivaldi oscillator units uniformly distributed in a circumferential direction of the Vivaldi oscillator array. The power divider includes multiple output ports in one-to-one correspondence with the multiple Vivaldi oscillator units. The multiple output ports of the power divider are coupled to the multiple Vivaldi oscillator units in a one-to-one correspondence.

Abstract: A method for placing, routing and using compute units and memory units in a reconfigurable computing grid includes receiving a placement graph for a computing task that defines a set of unplaced memory units, a set of unplaced compute units and data connections between the unplaced memory units and the unplaced compute units, the data connections comprising primary connections corresponding to the primary ports of the unplaced compute units and secondary connections corresponding to the secondary ports of the unplaced compute units. The method also includes forming a subgraph for each unplaced memory unit having a primary connection, each subgraph comprising the unplaced memory unit and each unplaced compute unit connected to the unplaced memory unit via a primary connection. The method also includes placing each formed subgraph as a cluster on the reconfigurable computing grid. A corresponding computer program product and system are also disclosed herein.

Abstract: Provided is a dual-polarized antenna. The dual-polarized antenna includes a horizontal radiating unit and a vertical radiating unit. The horizontal radiating unit includes a power divider and a Vivaldi oscillator array. The Vivaldi oscillator array includes multiple Vivaldi oscillator units uniformly distributed in a circumferential direction of the Vivaldi oscillator array. The power divider includes multiple output ports in one-to-one correspondence with the multiple Vivaldi oscillator units. The multiple output ports of the power divider are coupled to the multiple Vivaldi oscillator units in a one-to-one correspondence. The vertical radiating unit is disposed on one side of the horizontal radiating unit and includes a vertically-polarized oscillator.

Abstract: An implementation-quality synthesis process begins with a logical design of an integrated circuit and, through a series of steps, generates a fully synthesized physical design of the integrated circuit. One of the steps is clock synthesis, which generates the clock network for the integrated circuit. In certain embodiments, a method includes the following steps. A reduced clock synthesis process is applied, rather than the implementation-quality clock synthesis process. This generates a clock network for the logical design, which will be referred to as a proxy clock network because it is used as a proxy to estimate power consumption of the fully synthesized clock network. Because the reduced clock synthesis process runs much faster than the implementation-quality clock synthesis process, the front end designer may use these power estimates in the front end design process, including to explore different design variations in the logical design.

Abstract: The disclosure provides a wheel. The wheel includes: a rim (10), a surface of an axial end of the rim (10) forming a first connecting surface (11); a spoke (20), a part of a surface of an axial end of the spoke (20) forming a second connecting surface (21), wherein the spoke (20) is laser welded with the first connecting surface (11) by the second connecting surface (21); and a welding bead structure (100) for fixedly connecting the rim (10) and the spoke (20) is formed at a contact position between the first connecting surface (11) and the second connecting surface (21), and the welding bead structure (100) is formed by a part of the rim (10) and a part of the spoke (20) being melted and then connected.

Abstract: Provided is a dual-polarized antenna. The dual-polarized antenna includes a horizontal radiating unit and a vertical radiating unit. The horizontal radiating unit includes a power divider and a Vivaldi oscillator array. The Vivaldi oscillator array includes multiple Vivaldi oscillator units uniformly distributed in a circumferential direction of the Vivaldi oscillator array. The power divider includes multiple output ports in one-to-one correspondence with the multiple Vivaldi oscillator units. The multiple output ports of the power divider are coupled to the multiple Vivaldi oscillator units in a one-to-one correspondence. The vertical radiating unit is disposed on one side of the horizontal radiating unit and includes a vertically-polarized oscillator.

Abstract: Provided is a single-polarized antenna. This single-polarized antenna includes a power divider and a Vivaldi oscillator array. The Vivaldi oscillator array includes multiple Vivaldi oscillator units uniformly distributed in a circumferential direction of the Vivaldi oscillator array. The power divider includes multiple output ports in one-to-one correspondence with the multiple Vivaldi oscillator units. The multiple output ports of the power divider are coupled to the multiple Vivaldi oscillator units in a one-to-one correspondence.

Abstract: Disclosed is a design method for resisting a dynamic load in a high temperature pipeline. The method includes the following steps: a first calculation step, calculating to obtain a temperature deformation displacement of each point of the pipeline; a second calculation step, calculating to obtain a modal result of the pipeline and a dynamic response displacement of each point of the pipeline; a comprehensive analysis step, comprehensively analyzing the temperature deformation displacement and displacements of the vibration modes of respective orders of the pipeline to find a position at which a rigid constraint is required to be added, and applying the rigid constraint along a direction in which the temperature deformation displacement is not affected substantially; and a determination step, calculating a stress of the pipeline and a reaction force of the rigid constraint to determine whether the stress and the reaction force meet design requirements.

Abstract: Disclosed is a design method for resisting a dynamic load in a high temperature pipeline. The method includes the following steps: a first calculation step, calculating to obtain a temperature deformation displacement of each point of the pipeline; a second calculation step, calculating to obtain a modal result of the pipeline and a dynamic response displacement of each point of the pipeline; a comprehensive analysis step, comprehensively analyzing the temperature deformation displacement and displacements of the vibration modes of respective orders of the pipeline to find a position at which a rigid constraint is required to be added, and applying the rigid constraint along a direction in which the temperature deformation displacement is not affected substantially; and a determination step, calculating a stress of the pipeline and a reaction force of the rigid constraint to determine whether the stress and the reaction force meet design requirements.

Abstract: A miniature housing, in whose housing body there is located an element emitting or receiving electromagnetic radiation, comprises at least two electrical terminal means projecting laterally beyond the housing body. The passage side of the miniature housing, through which the element emits or receives, is oriented substantially perpendicularly to the mounting plane of the miniature housing. The electrical terminal means of the miniature housing projecting laterally beyond the housing body are connected electrically conductively to conductors, which bring about direct contacting with the emitting or receiving element. The contacting faces of the terminal means are thus arranged substantially perpendicular to the passage side of the miniature housing. As a result of this arrangement the miniature housing may be embedded at least in part in a support, such that the miniature housing is no longer of any significance to the thickness of a lighting device.

Abstract: A miniature housing, in whose housing body there is located an element emitting or receiving electromagnetic radiation, comprises at least two electrical terminal means projecting laterally beyond the housing body. The passage side of the miniature housing, through which the element emits or receives, is oriented substantially perpendicularly to the mounting plane of the miniature housing. The electrical terminal means of the miniature housing projecting laterally beyond the housing body are connected electrically conductively to conductors, which bring about direct contacting with the emitting or receiving element. The contacting faces of the terminal means are thus arranged substantially perpendicular to the passage side of the miniature housing. As a result of this arrangement the miniature housing may be embedded at least in part in a support, such that the miniature housing is no longer of any significance to the thickness of a lighting device.