Patents by Inventor Feng-Tsai Tsai

Feng-Tsai Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8502328
    Abstract: A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 6, 2013
    Assignee: Maxchip Electronics Corp.
    Inventors: Tsai-Chiang Nieh, Tung-Ming Lai, Feng-Tsai Tsai
  • Publication number: 20120153469
    Abstract: A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 21, 2012
    Applicant: MAXCHIP ELECTRONICS CORP.
    Inventors: Tsai-Chiang Nieh, Tung-Ming Lai, Feng-Tsai Tsai
  • Patent number: 8163583
    Abstract: A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: April 24, 2012
    Assignee: Maxchip Electronics Corp.
    Inventors: Tsai-Chiang Nieh, Tung-Ming Lai, Feng-Tsai Tsai
  • Publication number: 20110169106
    Abstract: A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.
    Type: Application
    Filed: March 10, 2010
    Publication date: July 14, 2011
    Applicant: MAXCHIP ELECTRONICS CORP.
    Inventors: Tsai-Chiang Nieh, Tung-Ming Lai, Feng-Tsai Tsai