Abstract: An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Abstract: A photolithography exposure of a photoresist coating on a semiconductor wafer uses an optical projection system to form a latent image. The photolithography exposure further uses a mask with a set of multiple pattern focus (MPF) marks. Each MPF mark of includes features having different critical dimension (CD) sizes. The latent image is developed to form a developed photoresist pattern. Dimension sizes are measured of features of the developed photoresist pattern corresponding to the features of the MPF marks having different CD sizes. A spatial focus map of the photolithography exposure is constructed based on the measured dimension sizes. To determine the focal distance at an MPF mark, ratios or differences may be determined between the measured dimension sizes corresponding to the features of the MPF marks having different CD sizes, and the focal distance at the location of the MFP mark constructed based on the determined ratios or differences.

Abstract: A router organizes an IC area into an array of global routing cells (GRCs) and generates a congestion map providing a separate congestion factor for each GRC boundary. The router then iteratively partitions the IC area into progressively smaller tiles while selecting a route for each net passing between tiles when possible without altering any previously routed net. The router thereafter iteratively merges the tiles into progressively larger tiles while selecting a route for each previously unrouted net residing wholly within a single tile, altering routes of previously routed nets when necessary to accommodate the selected route. When selecting each route for any connection of a net, the router seeks to minimize a cost function of congestion factors of all GRC boundaries.

Abstract: A router selects routes for nets interconnecting terminals of circuit devices within an area of an IC. The router organizes the IC area into an array of global routing cells (GRCs) and generates a congestion map providing a separate congestion factor for each GRC boundary that is a probabilistic measure of an estimated percentage of a capacity of the GRC boundary that will be occupied by nets when all nets have been routed. The router then iteratively partitions the IC area into progressively smaller tiles until the tiles reach a predetermined minimum size. Between partitioning iterations, the router selects a route for each net passing between tiles when possible to do so without altering any previously routed net. The router thereafter iteratively merges the tiles into progressively larger tiles.

Abstract: The present invention provides An alternating phase shifting mask (Alt-PSM), that is to be used in a double exposure lithographic process with a light source of 248 nm. The Alt-PSM comprises: (1) a quartz substrate; (2) at least one semi-dense line on the substrate, wherein the semi-dense line is adjacent to a clear region with a width larger than 2 nm on one side and on the other side is adjacent to a dense-line pattern with a narrow pitch; (3) a first phase shifting region, which is located between the dense line pattern and the semi-dense line pattern and is adjacent to the semi-dense line; and (4) a second phase shifting region with a predetermined width, which is adjacent to the semi-dense line and located on the side opposite to the first phase shifting region; wherein the phase difference between the first phase shifting region and the second phase shifting region is 180 degree.

Abstract: The present invention provides An alternating phase shifting mask (Alt-PSM), that is to be used in a double exposure lithographic process with a light source of 248 nm. The Alt-PSM comprises: (1) a quartz substrate; (2) at least one semi-dense line on the substrate, wherein the semi-dense line is adjacent to a clear region with a width larger than 2 nm on one side and on the other side is adjacent to a dense-line pattern with a narrow pitch; (3) a first phase shifting region, which is located between the dense line pattern and the semi-dense line pattern and is adjacent to the semi-dense line; and (4) a second phase shifting region with a predetermined width, which is adjacent to the semi-dense line and located on the side opposite to the first phase shifting region; wherein the phase difference between the first phase shifting region and the second phase shifting region is 180 degree.

Abstract: A method of modifying a photo mask pattern by using computer aided design (CAD) is described. The photo mask pattern is used to manufacture a photo mask for transferal to a photoresist layer formed on a surface of a semiconductor wafer so as to form a predetermined original pattern. A first modification is first performed according to an optic proximity effect, and then a second modification is performed according to a line end shortening effect. The present invention prevents the line end shortening effect from occurring in a subsequent trim down etching process of the original pattern performed for reducing its critical dimension.