Patents by Inventor Feng-Yuan Chiu
Feng-Yuan Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9983473Abstract: A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.Type: GrantFiled: February 17, 2017Date of Patent: May 29, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Yu Lin, Yi-Jie Chen, Feng-Yuan Chiu, Ying-Chou Cheng, Kuei-Liang Lu, Ya-Hui Chang, Ru-Gun Liu, Tsai-Sheng Gau
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Publication number: 20170160633Abstract: A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.Type: ApplicationFiled: February 17, 2017Publication date: June 8, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Yu LIN, Yi-Jie CHEN, Feng-Yuan CHIU, Ying-Chou CHENG, Kuei-Liang LU, Ya-Hui CHANG, Ru-Gun LIU, Tsai-Sheng GAU
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Patent number: 9612526Abstract: A photomask and method for fabricating an integrated circuit is provided. The photomask includes a plurality of main features, enclosed in at least one first region and at least one second region, wherein the first region comprises single the main feature and the second region comprises multiple the main features; and a plurality of assistant features disposed between the first region and the second region, or between the second regions. The photomask enhances the accuracy of the critical dimension and facilitate fabricating an integrated circuit.Type: GrantFiled: August 28, 2014Date of Patent: April 4, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Yu Lin, Yi-Jie Chen, Feng-Yuan Chiu, Ying-Chou Cheng, Kuei-Liang Lu, Ya-Hui Chang, Ru-Gun Liu, Tsai-Sheng Gau
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Patent number: 9367655Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.Type: GrantFiled: April 10, 2012Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chang Shih, Chung-min Fu, Ying-Chou Cheng, Yung-Fong Lu, Feng-Yuan Chiu, Chiu Hsiu Chen
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Publication number: 20160062226Abstract: A photomask and method for fabricating an integrated circuit is provided. The photomask includes a plurality of main features, enclosed in at least one first region and at least one second region, wherein the first region comprises single the main feature and the second region comprises multiple the main features; and a plurality of assistant features disposed between the first region and the second region, or between the second regions. The photomask enhances the accuracy of the critical dimension and facilitate fabricating an integrated circuit.Type: ApplicationFiled: August 28, 2014Publication date: March 3, 2016Inventors: Chun-Yu LIN, Yi-Jie CHEN, Feng-Yuan CHIU, Ying-Chou CHENG, Kuei-Liang LU, Ya-Hui CHANG, Ru-Gun LIU, Tsai-Sheng GAU
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Patent number: 9159577Abstract: According to an exemplary embodiment, a method of forming a substrate pattern having an isolated region and a dense region is provided. The method includes the following operations: forming a first photoresist layer over the substrate; exposing the first photoresist layer through a first mask corresponding to the isolated region; developing the first photoresist layer to form a first pattern; forming a second photoresist layer over the substrate and the first pattern; exposing the second photoresist layer through a second mask corresponding to the substrate pattern; developing the second photoresist layer to form a second pattern; and etching the first pattern and the substrate to form the substrate pattern in the isolated region and the dense region.Type: GrantFiled: February 14, 2014Date of Patent: October 13, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Yu Lin, Feng-Yuan Chiu, Bing-Syun Yeh, Yi-Jie Chen, Ying-Chou Cheng, I-Chang Shih, Ru-Gun Liu, Shih-Ming Chang
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Publication number: 20150235857Abstract: According to an exemplary embodiment, a method of forming a substrate pattern having an isolated region and a dense region is provided. The method includes the following operations: forming a first photoresist layer over the substrate; exposing the first photoresist layer through a first mask corresponding to the isolated region; developing the first photoresist layer to form a first pattern; forming a second photoresist layer over the substrate and the first pattern; exposing the second photoresist layer through a second mask corresponding to the substrate pattern; developing the second photoresist layer to form a second pattern; and etching the first pattern and the substrate to form the substrate pattern in the isolated region and the dense region.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHUN-YU LIN, FENG-YUAN CHIU, BING-SYUN YEH, YI-JIE CHEN, YING-CHOU CHENG, I-CHANG SHIH, RU-GUN LIU, SHIH-MING CHANG
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Patent number: 8952329Abstract: A method for characterizing a three-dimensional surface profile of a semiconductor workpiece is provided. In this method, the three-dimensional surface profile is imaged from a normal angle to measure widths of various surfaces in a first image. The three-dimensional surface is also imaged from a first oblique angle to re-measure the widths of the various surfaces in a second image. Based on differences in widths of corresponding surfaces for first and second images, a feature height and sidewall angle are determined for the three-dimensional profile.Type: GrantFiled: October 3, 2013Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Chang Shih, Yi-Jie Chen, Chia-Cheng Chang, Feng-Yuan Chiu, Ying-Chou Cheng, Chiu Hsiu Chen, Bing-Syun Yeh, Ru-Gun Liu
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Patent number: 8910092Abstract: Integrated circuit design techniques are disclosed. In some methods, a target layout design having a geometric pattern thereon is received. A set of fast-bias contour (FBC) rules is applied to the target layout design to provide an electronic photomask having FBC-edits. The FBC-edits differentiate the electronic photomask from the target layout design, and the FBC rules are applied without previously applying optical proximity correction (OPC) to the target layout design. A lithography process check is performed on the electronic photomask to determine whether a patterned integrated circuit layer, which is to be manufactured based on the electronic photomask, is expected to be in conformance with the geometric pattern of the target layout design.Type: GrantFiled: November 13, 2013Date of Patent: December 9, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Chang Shih, Feng-Yuan Chiu, Ying-Chou Cheng, Chiu Hsiu Chen, Ru-Gun Liu
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Publication number: 20130267047Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.Type: ApplicationFiled: April 10, 2012Publication date: October 10, 2013Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: I-Chang Shih, Chung-min Fu, Ying-Chou Cheng, Yung-Fong Lu, Feng-Yuan Chiu, Chiu Hsiu Chen
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Patent number: 8103978Abstract: A method for establishing a scattering bar rule for a mask pattern for fabricating a device is provided. The method is described as follows. First, at least one image simulation model is established according to the mask pattern and a process reference set used for fabricating the device based on the mask pattern. Next, a plurality of scattering bar reference sets is applied to the image simulation model so as to generate a plurality of simulation images, respectively. Further, a portion of the simulation images are selected to be a plurality of candidate layouts according to a screening criterion. Next, one of the candidate layouts is determined to be a pattern layout according to a selection rule, and the scattering bar reference set corresponding to the pattern layout is determined to be a scattering bar rule of the mask pattern.Type: GrantFiled: August 26, 2008Date of Patent: January 24, 2012Assignee: ProMOS Technologies Inc.Inventors: Chun-Yu Lin, Chia-Jung Liou, Cheng-Hung Ku, Feng-Yuan Chiu, Chun-Kuang Lin, Chih-Chiang Huang
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Publication number: 20090276750Abstract: A method for establishing a scattering bar rule for a mask pattern for fabricating a device is provided. The method is described as follows. First, at least one image simulation model is established according to the mask pattern and a process reference set used for fabricating the device based on the mask pattern. Next, a plurality of scattering bar reference sets is applied to the image simulation model so as to generate a plurality of simulation images, respectively. Further, a portion of the simulation images are selected to be a plurality of candidate layouts according to a screening criterion. Next, one of the candidate layouts is determined to be a pattern layout according to a selection rule, and the scattering bar reference set corresponding to the pattern layout is determined to be a scattering bar rule of the mask pattern.Type: ApplicationFiled: August 26, 2008Publication date: November 5, 2009Applicant: PROMOS TECHNOLOGIES INC.Inventors: Chun-Yu Lin, Chia-Jung Liou, Cheng-Hung Ku, Feng-Yuan Chiu, Chun-Kuang Lin, Chih-Chiang Huang