Patents by Inventor Fengchao MA

Fengchao MA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10178776
    Abstract: A method for wiring differential signal lines and a PCB are disclosed. The wiring method includes: providing a rectangle-shaped glass fiber fabric formed of glass fibers which are woven and interlaced with each other and an adhesive filled therebetween; determining a wiring direction and obtaining a glass fiber bundle number of the glass fiber fabric in the wiring direction; equally dividing the glass fiber fabric into glass fiber units, and obtaining a width of each glass fiber unit according to a size of the glass fiber fabric in a direction perpendicular to the wiring direction and the number of the glass fiber units; determining a line distance and line widths of the differential signal lines; and according to the line distance and the line widths, forming the differential signal lines on a metal layer along the wiring direction to make the differential signal lines meet predetermined requirements.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: January 8, 2019
    Assignee: ZTE CORPORATION
    Inventors: Tao Guo, Fengchao Ma, Yuanwang Zhang
  • Patent number: 10064271
    Abstract: The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 28, 2018
    Assignee: ZTE CORPORATION
    Inventors: Bi Yi, Fengchao Ma, Yonghui Ren, Wang Xiong, Yingxin Wang
  • Publication number: 20170325334
    Abstract: A method for wiring differential signal lines and a PCB are disclosed. The wiring method includes: providing a rectangle-shaped glass fiber fabric formed of glass fibers which are woven and interlaced with each other and an adhesive filled therebetween; determining a wiring direction and obtaining a glass fiber bundle number of the glass fiber fabric in the wiring direction; equally dividing the glass fiber fabric into glass fiber units, and obtaining a width of each glass fiber unit according to a size of the glass fiber fabric in a direction perpendicular to the wiring direction and the number of the glass fiber units; determining a line distance and line widths of the differential signal lines; and according to the line distance and the line widths, forming the differential signal lines on a metal layer along the wiring direction to make the differential signal lines meet predetermined requirements.
    Type: Application
    Filed: May 13, 2015
    Publication date: November 9, 2017
    Applicant: ZTE CORPORATION
    Inventors: Tao GUO, Fengchao MA, Yuanwang ZHANG
  • Publication number: 20160323995
    Abstract: The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 3, 2016
    Inventors: Bi YI, Fengchao MA, Yonghui REN, Wang XIONG, Yingxin WANG