Abstract: The present invention relates to the field of water surface treatment, and in particular to a cleaning ship for water surface treatment for harvesting water plants. In order to solve the technical problems that the existing cleaning ship cannot adapt to the waters of different depths for harvesting water plants, and a hull has low load utilization rate for the collected water plants and affects the overall working efficiency and the fuel economy of the hull, the present invention provides a cleaning ship for water surface treatment for harvesting water plants, comprising a steel belt conveying mechanism, a driven shaft and the like. The steel belt conveying mechanism drives the driven shaft to rotate.

Abstract: The present invention relates to the technical field of water surface waste treatment, and in particular to a water surface floater collecting ship. The technical problems are: picking up floaters with the cooperation of labors consumes manpower and causes disturbance of water surface, which makes the floaters float further away with water waves, and the odor emitted by the collected floating waste will pollute the environment and affect the salvage efficiency. The technical solution is: a water surface floater collecting ship, comprising a hull, a collecting system, etc.; the left part of the hull is connected with the collecting system used for collecting waste.

Abstract: A ReRAM memory array includes ReRAM memory cells and a select circuit having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.

Abstract: A method for erasing a ReRAM memory cell that includes a ReRAM device having a select circuit with two series-connected select transistors. The method includes determining if the ReRAM cell is selected for erasing. If the ReRAM cell is selected for erasing, the bit line node is biased at a first voltage potential, the source line node is biased at a second voltage potential greater than the first voltage potential and the gates of the series-connected select transistors are supplied with positive voltage pulses. The difference between the first voltage potential and the second voltage potential is sufficient to erase the ReRAM device in the ReRAM cell. If the ReRAM cell is unselected for erasing, the gate of the one of the series-connected select transistors having its drain connected to an electrode of the ReRAM device is supplied with a voltage potential insufficient to turn it on.

Abstract: A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.

Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

Abstract: A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.

Abstract: A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.

Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.

Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.

Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

Abstract: A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.

Abstract: A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.

Abstract: A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.

Abstract: A high-voltage transistor includes an active region including a diffused region of a first conductivity type defined by inner edges of a border of shallow trench isolation. A gate having side edges and end edges is disposed over the active region. Spaced apart source and drain regions of a second conductivity type opposite the first conductivity type are disposed in the active region outwardly with respect to the side edges of the gate. Lightly-doped regions of the second conductivity type more lightly-doped than the source and drain regions surround the source and drain regions and extend inwardly between the source and drain regions towards the gate to define a channel, and outwardly towards all of the inner edges of the shallow trench isolation. Outer edges of the lightly-doped region from at least the drain region are spaced apart from the inner edges of the shallow trench isolation.

Abstract: A high-voltage transistor includes an active region including a diffused region of a first conductivity type defined by inner edges of a border of shallow trench isolation. A gate having side edges and end edges is disposed over the active region. Spaced apart source and drain regions of a second conductivity type opposite the first conductivity type are disposed in the active region outwardly with respect to the side edges of the gate. Lightly-doped regions of the second conductivity type more lightly-doped than the source and drain regions surround the source and drain regions and extend inwardly between the source and drain regions towards the gate to define a channel, and outwardly towards all of the inner edges of the shallow trench isolation. Outer edges of the lightly-doped region from at least the drain region are spaced apart from the inner edges of the shallow trench isolation.