Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.

Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

Abstract: A method for removing a patterned negative photoresist from a substrate includes: (a) placing the substrate on lift pins of a wafer chuck; (b) retracting the lift pins to place the substrate in a pin-down position and concurrently heating the substrate to a first temperature not exceeding 100° C.; (c) raising the lift pins to place the substrate in a pin-up position; (d) generating a plasma from a gas comprising NH3; and (e) exposing the substrate to the plasma in the pin-up position and the pin-down position alternatively to selectively remove the negative photoresist from the substrate.

Abstract: A method of forming semiconductor memory device including following steps. Firstly, a substrate having a memory cell region and a peripheral region is provided, and a first semiconductor layer is formed on the substrate within the periphery region. Next, an insulating layer and a second semiconductor layer are formed on the substrate, and the second semiconductor layer covers the substrate, the first semiconductor layer and the insulating layer. Then, a sacrificial layer is formed on the second semiconductor layer, wherein top surfaces of the sacrificial layer within the memory cell region and the periphery region are coplanar. Following these, a removing process is performed to remove the sacrificial layer, the second semiconductor layer and the insulating layer, to expose the first semiconductor layer. After that, a top surface of the first semiconductor layer is leveled with a top surface of the second semiconductor layer.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first buried gate and a second buried gate in the substrate on the memory region; forming a first silicon layer on the substrate on the periphery region; forming a stacked layer on the first silicon layer; forming an epitaxial layer on the substrate between the first buried gate and the second buried gate; and forming a second silicon layer on the epitaxial layer on the memory region and the stacked layer on the periphery region.

Abstract: A manufacturing method of a semiconductor storage device includes forming a plurality of bit line structures on a semiconductor substrate and forming a plurality of storage node contacts disposed between the bit line structures. The method of forming the storage node contacts includes forming a plurality of conductive patterns on the semiconductor substrate followed by performing an etching back process to the conductive patterns for decreasing a thickness of the conductive patterns. The manufacturing method further includes forming a plurality of isolation patterns between the conductive patterns, wherein the isolation patterns are formed after forming the plurality of conductive patterns and before the etching back process. According to the present invention, the storage node contacts are formed by first forming the conductive patterns and then forming the isolation patterns between the conductive patterns, so as to simplify manufacturing process and increase process yield.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first buried gate and a second buried gate in the substrate on the memory region; forming a first silicon layer on the substrate on the periphery region; forming a stacked layer on the first silicon layer; forming an epitaxial layer on the substrate between the first buried gate and the second buried gate; and forming a second silicon layer on the epitaxial layer on the memory region and the stacked layer on the periphery region.