Abstract: A device for detection of a display panel is provided in the embodiments of the disclosure, which is configured to detect signal lines on the display panel. The signal lines at least comprises a plurality of data lines which are divided into N groups; the device comprises: N shorting bars provided within an electrode lead region of the display panel to intersect the plurality of data lines, a plurality of welding pads provided on both sides of the electrode lead region, each of which shorting bars short-circuits one of the N groups of data lines together and connects with two welding pad at both ends thereof respectively, and a switch which is provided between each of the shorting bars and each of the corresponding welding pads connecting with the former on one and the same side of all the shorting bars; and N is a positive integer not less than.

Abstract: An array substrate motherboard includes a substrate including a plurality of gate lines, a plurality of gate line driving leads, a plurality of data lines, and a plurality of data line driving leads; a plurality of gate line testing leads; a plurality of data line testing leads and a plurality of data line driving leads; a plurality of gate line testing pads; a plurality of data line testing pads; and an insulating layer arranged between the data line testing leads and the data line driving leads in the trimming region. A respective one of the plurality of data line testing pads is connected with a respective one of the plurality of data line testing leads. A respective one of the plurality of data line driving leads is connected with one of the plurality of data line testing leads that penetrate through the insulating layer.

Abstract: An array substrate motherboard includes a substrate including a plurality of gate lines, a plurality of gate line driving leads, a plurality of data lines, and a plurality of data line driving leads; a plurality of gate line testing leads; a plurality of data line testing leads and a plurality of data line driving leads; a plurality of gate line testing pads; a plurality of data line testing pads; and an insulating layer arranged between the data line testing leads and the data line driving leads in the trimming region. A respective one of the plurality of data line testing pads is connected with a respective one of the plurality of data line testing leads. A respective one of the plurality of data line driving leads is connected with one of the plurality of data line testing leads that penetrate through the insulating layer.

Abstract: In some embodiments, an array substrate motherboard and a fabricating method thereof are provided. The method includes: providing a substrate including multiple gate lines, gate driving leads, data lines, and data driving leads, each gate line corresponds to one gate driving lead, each data line corresponds to one data driving lead; forming multiple gate line testing leads, each gate line testing lead is connected with a gate driving lead; forming multiple data line testing leads, each data line testing lead is connected with a subset of the multiple data driving leads; forming multiple gate line testing pads, each gate line testing pad is connected with a gate line testing lead; forming multiple data line testing pads, each data line testing pad is connected with two data line testing leads; and using the gate line testing pads and gate line testing pads to test the gate lines and data lines.

Abstract: A device for detection of a display panel is provided in the embodiments of the disclosure, which is configured to detect signal lines on the display panel. The signal lines at least comprises a plurality of data lines which are divided into N groups; the device comprises: N shorting bars provided within an electrode lead region of the display panel to intersect the plurality of data lines, a plurality of welding pads provided on both sides of the electrode lead region, each of which shorting bars short-circuits one of the N groups of data lines together and connects with two welding pad at both ends thereof respectively, and a switch which is provided between each of the shorting bars and each of the corresponding welding pads connecting with the former on one and the same side of all the shorting bars; and N is a positive integer not less than.

Abstract: In some embodiments, an array substrate motherboard and a fabricating method thereof are provided. The method includes: providing a substrate including multiple gate lines, gate driving leads, data lines, and data driving leads, each gate line corresponds to one gate driving lead, each data line corresponds to one data driving lead; forming multiple gate line testing leads, each gate line testing lead is connected with a gate driving lead; forming multiple data line testing leads, each data line testing lead is connected with a subset of the multiple data driving leads; forming multiple gate line testing pads, each gate line testing pad is connected with a gate line testing lead; forming multiple data line testing pads, each data line testing pad is connected with two data line testing leads; and using the gate line testing pads and gate line testing pads to test the gate lines and data lines.

Abstract: The present application discloses a display panel test structure for testing whether signal lines of a display panel are defective, the signal lines at least comprising a plurality of data lines which are divided into N groups, the display panel test structure comprising N first shorting bars arranged in a test area of the display panel, each of which being configured to short-circuit a group of data lines, wherein the display panel test structure further comprises a plurality of first test pads arranged in the test area, each of which connects with one shorting bar corresponding thereto, and each of the first test pads is configured to load a signal to a group of data lines corresponding thereto during a test.

Abstract: The present application discloses a display panel test structure for testing whether signal lines of a display panel are defective, the signal lines at least comprising a plurality of data lines which are divided into N groups, the display panel test structure comprising N first shorting bars arranged in a test area of the display panel, each of which being configured to short-circuit a group of data lines, wherein the display panel test structure further comprises a plurality of first test pads arranged in the test area, each of which connects with one shorting bar corresponding thereto, and each of the first test pads is configured to load a signal to a group of data lines corresponding thereto during a test.