Abstract: A transistor is disclosed, comprising: a layer of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion; a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material; a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material; a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and a layer of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material.

Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.

Abstract: A signal measuring apparatus comprising: signal circuitry configured to receive an input signal to be measured; and memory circuitry coupled to the signal circuitry and configured to store information representing a magnitude of a voltage or a current of the input signal; wherein the memory circuitry comprises a first memory cell having a material which is arranged to switch from a first material state to a second material state in response to a first switching signal being applied thereto, wherein the first memory cell is tuned to a first value for the first switching signal so that a current or voltage with a magnitude at or above the first value will cause the material of the first memory cell to switch from the first material state to second material state; wherein the apparatus is configured to apply a measurement signal indicative of the input signal to the first memory cell for switching the material of the first memory cell from the first material state to the second material state in dependence on a

Abstract: A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.

Abstract: A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.

Abstract: A method of manufacturing an electronic circuit comprising a first device and at least a second device is disclosed. The first device comprises a first terminal, a second terminal, and a first body of semiconductive material providing a semiconductive path between the first and second terminals, and the second device comprises a third terminal, a fourth terminal, and a second body of material providing a resistive or semiconductive current path between the third terminal and the fourth terminal. The method comprises: forming the first body; and forming the second body, wherein the first body comprises a first quantity of a metal oxide and the second body comprises a second quantity of said metal oxide. Corresponding electronic circuits are disclosed.

Abstract: A transistor is disclosed, comprising: a layer of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion; a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material; a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material; a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and a layer of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material.

Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.

Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.

Abstract: A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.

Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.

Abstract: A transistor is disclosed, comprising: a layer of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion; a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material; a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material; a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and a layer of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material.