Abstract: An integrated circuit memory array having a plurality of memory cells including two cross-coupled transistors of one conductivity type, load transistors of the other conductivity type, and a bit line, connected to the base region of one of the cross-coupled transistors through a bit line transistor. The array features a common node, directly interconnecting all of the base regions of the load transistors and the emitter regions of the cross-coupled transistors, for each of the memory cells; and a row selection line connected to the emitter regions of the load transistors in an associated row of memory cells.