Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs is described. Each FeFET comprises a gate stack, a source, a drain, a channel and a bulk substrate region, where the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel. A positive or a negative voltage is applied to the source and drain regions of at least one FeFET memory cell depending on the channel type. The gate and bulk substrate regions are held at a ground state during said applying of the positive voltage to the source and drain regions of the FeFET memory cell to cause erasure of the at least one FeFET memory cell. In addition, a FeFET is described with a charge storage layer disposed adjacently to the ferroelectric layer within the gate stack.

Abstract: A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs is described. Each FeFET comprises a gate stack, a source, a drain, a channel and a bulk substrate region, where the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel. A positive or a negative voltage is applied to the source and drain regions of at least one FeFET memory cell depending on the channel type. The gate and bulk substrate regions are held at a ground state during said applying of the positive voltage to the source and drain regions of the FeFET memory cell to cause erasure of the at least one FeFET memory cell. In addition, a FeFET is described with a charge storage layer disposed adjacently to the ferroelectric layer within the gate stack.

Abstract: A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs is described. Each FeFET comprises a gate stack, a source, a drain, a channel and a bulk substrate region, where the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel. A positive or a negative voltage is applied to the source and drain regions of at least one FeFET memory cell depending on the channel type. The gate and bulk substrate regions are held at a ground state during said applying of the positive voltage to the source and drain regions of the FeFET memory cell to cause erasure of the at least one FeFET memory cell. In addition, a FeFET is described with a charge storage layer disposed adjacently to the ferroelectric layer within the gate stack.

Abstract: An apparatus is provided. The apparatus has an interface for receiving media information, wherein the media information indicates a segment data rate for each of a plurality of media data segments and further indicates a quality value for each of the plurality of media data segments. Moreover, the apparatus has a processor for selecting one or more selected segments from the plurality of the media data segments depending on the segment data rates of the plurality of media data segments, depending on the quality values of the plurality of media data segments and depending on an available data rate of a communication resource. The interface is configured to transmit a request requesting the one or more selected segments. Moreover, the interface is configured to receive the one or more selected segments being transmitted on the communication resource.

Abstract: A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs is described. Each FeFET comprises a gate stack, a source, a drain, a channel and a bulk substrate region, where the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel. A positive or a negative voltage is applied to the source and drain regions of at least one FeFET memory cell depending on the channel type. The gate and bulk substrate regions are held at a ground state during said applying of the positive voltage to the source and drain regions of the FeFET memory cell to cause erasure of the at least one FeFET memory cell. In addition, a FeFET is described with a charge storage layer disposed adjacently to the ferroelectric layer within the gate stack.

Abstract: An integrated circuit includes a ferroelectric memory cell. In one embodiment, the ferroelectric memory cell includes a first oxide storage layer, a second oxide storage layer, and an amorphous layer disposed between the first and second oxide storage layers. Each of the first and second oxide storage layers includes a ferroelectric material that is at least partially in a ferroelectric state and further includes, as main components, oxygen and any of the group consisting of Hf, Zr and (Hf,Zr).

Abstract: An integrated circuit includes a ferroelectric memory cell. In one embodiment, the ferroelectric memory cell includes a first oxide storage layer, a second oxide storage layer, and an amorphous layer disposed between the first and second oxide storage layers. Each of the first and second oxide storage layers includes a ferroelectric material that is at least partially in a ferroelectric state and further includes, as main components, oxygen and any of the group consisting of Hf, Zr and (Hf,Zr).

Abstract: The cleaning device for the exhaust gas turbine comprises openings, which open out into the flow duct upstream of the nozzle ring, for injecting a cleaning liquid from the radially inner side into the annular flow duct, a cavity, which is connected to the openings, for distributing the cleaning liquid to the openings, and a supply line for supplying the cleaning liquid to the cavity. The cleaning device according to the invention provides a uniform distribution of water to nozzle ring or to the rotor blades of the turbine rotor wheel.