Abstract: The present disclosure includes vertical 3D DRAM array with digitline select circuitry and digitline decoupling operation, array select circuitry connected to the 3D DRAM array and methods of memory operation relating to read reference setting, read window development, and latch firing. An example memory device comprises a first array of vertically stacked memory cells and a first digitline connected to the access devices in the first array. A second digitline is connected to and decoupled from the first digitline by select circuitry. The select circuitry comprises a first digitline multiplexer and a bleed transistor. The first digitline is connected to a shared first source/drain region of the first digitline multiplexer and the bleed transistor. The select circuitry further comprises a source follower transistor and a second digitline multiplexer. The first digitline is connected to a gate of the source follower transistor.

Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

Abstract: Methods, systems, and devices for memory array seasoning are described. Some memory cells may have an undesirably high threshold voltage and thus a seasoning operation may be performed on a target memory cell. To season the target memory cell, a bit line and a word line associated with the cell may be activated. Additionally or alternatively, a word line coupled with a second memory cell (e.g., a helper memory cell) that shares the activated bit line may be activated. Accordingly, current flowing across the target memory cell may be increased, which may reduce its threshold voltage.

Abstract: Methods, systems, and devices for a sensing circuit in a vertical memory system are described. An apparatus may include a set of memory cells each coupled with a respective pillar of a set of pillars. A set of transistors, each of which is coupled with a digit line common to the set of memory cells, may be coupled with a respective pillar of the set of pillars. A first transistor of the set of transistors may include a first terminal coupled with a first bias line and a first pillar of the set of pillars, and may include a second terminal coupled with the digit line. A second transistor of the set of transistors may include a first terminal coupled with a second bias line and a second pillar of the set of pillars, and may include a gate terminal coupled with the digit line.

Abstract: Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.

Abstract: Methods, systems, and devices related to counter-based sense amplifier method for memory cells are described. The counter-based read algorithm may comprise the following phases: storing in a counter associated to an array of memory cells the value of the number of bits having a predetermined logic value of the data bits stored in the memory array; reading from said counter the value corresponding to the number of bits having the predetermined logic value; reading the data stored in the array of memory cells by applying a ramp of biasing voltages; counting the number of bits having the predetermined logic value during the data reading phase; stopping the data reading phase when the number of bits having the predetermined logic value is equal to the value stored in said counter.

Abstract: A memory apparatus and a method for operating the same. The method includes performing a read operation on a set of memory cells, detecting an error in data read from the set of memory cells based on an error correction code (ECC) operation performed on the data, and performing a scrubbing operation or a refreshing operation on the set of memory cells according to a detecting result.

Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.

Abstract: Systems, methods, and apparatus for a memory device. In one approach, known reference patterns are stored in a memory array. The patterns are associated with codewords stored in the memory array. A first pattern has all memory cells written to a first logic state (e.g., all logic ones), and a second pattern has all memory cells written to an opposite second logic state (e.g., all logic zeros). When a controller reads a codeword, the controller first reads memory cells of the associated reference patterns to determine data for estimating a threshold voltage distribution of memory cells in the codeword. Based on a number of memory cells of the reference patterns that snap when reading the first and second patterns, the controller selects a read voltage for reading the associated codeword.

Abstract: In some implementations, a memory system controller may receive a data block that is associated with a first codeword having a first data portion and a first parity portion, and a second codeword having a second data portion, a second parity portion, and a metadata portion. The memory system controller may detect and correct one or more errors at one or more symbol locations in the first codeword using information in the first codeword. The memory system controller may set one or more erasure conditions at one or more symbol locations in the second codeword that share a positional relationship with the one or more symbol locations in the first codeword having the one or more errors. The memory system controller may correct the one or more erasure conditions at the one or more symbol locations in the second codeword using information in the second codeword.

Abstract: It is disclosed a memory device comprising a plurality of memory cells arranged in a three-dimensional array having a plurality of levels above a substrate, comprising a plurality of conductive word lines extending over a respective level and coupled to said plurality of memory cells, each word line being connected to a respective step of a staircase positioned in a staircase area (306, 710) outside an active area (702) of the array of the plurality of memory cells. The memory device further comprises a plurality of word line drivers (500) for the corresponding plurality of word lines, comprises a first plurality of Through Array Via elements (305; 305a, 305b, 305c, 305d) for the corresponding plurality of word lines and comprises a second plurality of Through Array Via elements (310; 310a, 310b, 310c, 301d) for the corresponding plurality of word lines.

Abstract: It is disclosed a memory device comprising a plurality of memory cells arranged in a three-dimensional array having a plurality of levels above a substrate, comprising a plurality of conductive word lines extending over a respective level and coupled to said plurality of memory cells, each word line being connected to a respective step of a staircase positioned in a staircase area (306, 710) outside an active area (702) of the array of the plurality of memory cells. The memory device further comprises a plurality of word line drivers (500) for the corresponding plurality of word lines and comprises a plurality of Through Array Via elements (305; 305a, 305b, 305c, 305d) for the corresponding plurality of word lines. The plurality of word line drivers and the plurality of Through Array Via elements are positioned in the staircase area (306).

Abstract: A memory device includes a memory array with a plurality of memory cells formed at respective intersections of a plurality of wordlines and a plurality of bit lines. The memory device further includes a page buffer circuit coupled to the memory array, the page buffer circuit comprising sense circuitry to measure a cell current read from a bitline of the plurality of bitlines and tail current bias circuitry coupled to the bitline, wherein the tail current bias circuitry comprises a tail current capacitor having a first terminal coupled to the bitline, the tail current capacitor to generate a tail current in the bitline during a signal integration period when the sense circuitry measures the cell current read from the bitline.

Abstract: A method including storing user data in memory cells of a memory array, storing, in a counter associated to the memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data, applying the read voltage to the cells of the counter to read the count data and to provide a target value corresponding to the number of bits in the user data having the first logic value. During the application of the read voltage, the count data and the user data are read simultaneously such that the target value is provided during the reading of the user data. The application of the read voltage is stopped when the number of bits in the user data having the first logic value corresponds to the target value.

Abstract: Methods, systems, and devices for word line charge integration are described. In some examples, a memory device may include a plurality of memory cells that are coupled with a word line and respective digit lines. During a read operation, the word line may be activated (e.g., driven to a voltage) and a subset of the respective digit lines may be activated (e.g., driven to a voltage) to begin integrating charges of each of the memory cells. Before each digit line is activated, the word line may be deactivated and the remaining digit lines may be activated (e.g., driven to a voltage) to begin integrating charges of the remaining memory cells that are coupled with the word line. After each of the digit lines are selected, respective sense components may be activated to sense the charges associated with the memory cells.

Abstract: Systems, methods, and apparatus for a memory device. In one approach, known reference patterns are stored in a memory array. The patterns are associated with codewords stored in the memory array. A first pattern has all memory cells written to a first logic state (e.g., all logic ones), and a second pattern has all memory cells written to an opposite second logic state (e.g., all logic zeros). When a controller reads a codeword, the controller first reads memory cells of the associated reference patterns to determine data for estimating a threshold voltage distribution of memory cells in the codeword. Based on a number of memory cells of the reference patterns that snap when reading the first and second patterns, the controller selects a read voltage for reading the associated codeword.

Abstract: It is disclosed a memory device comprising: a plurality of pillars extending through a plurality of levels of a memory array; one or more memory cells of the memory array coupled with a respective pillar and a respective word line at each level; a digit line; a plurality of TFTs, each TFT being configured to selectively couple the digit line with a respective pillar, wherein the plurality of pillars, the one or more memory cells and the plurality of thin film transistors are positioned in a first area of the memory array, and wherein the digit line extends in the first area and at least partially in a second area outside the first area; a driver for the digit line. The driver comprises a first TFT, a second TFT and a pillar, wherein the first TFT, the second TFT and the pillar are positioned in the second area.

Abstract: Methods, systems, and devices for a counter-based sense amplifier method for memory cells are described. The described techniques provide for a memory system to store, in a counter associated with an array of memory cells, a value indicating a quantity of memory cells in the array having a predetermined logic value. The memory system may perform a read operation to read the data stored in the array of memory cells by applying a ramping bias voltage and may count the quantity of memory cells having the predetermined logic value during the read operation. The memory system may stop the read operation when the memory system identifies a quantity of memory cells having the predetermined logic value that is equal to the value stored to the counter.

Abstract: Methods, systems, and devices for threshold voltage compensation for a memory system sense amplifier are described. A sense amplifier may include a first transistor comprising: a gate terminal coupled with a second digit line, a drain terminal coupled with a first digit line through a first switching component, and a source terminal coupled with a node. The sense amplifier may include a second transistor comprising a source terminal coupled with the node. The sense amplifier may include a first voltage supply configured to be coupled with the node using a third transistor during an amplification phase of a sense operation for the memory cell; and a second voltage supply configured to be coupled with the node through a fourth transistor during a compensation phase of the sense operation.

Abstract: Methods, systems, and devices for memory array seasoning are described. Some memory cells may have an undesirably high threshold voltage and thus a seasoning operation may be performed on a target memory cell. To season the target memory cell, a bit line and a word line associated with the cell may be activated. Additionally or alternatively, a word line coupled with a second memory cell (e.g., a helper memory cell) that shares the activated bit line may be activated. Accordingly, current flowing across the target memory cell may be increased, which may reduce its threshold voltage.