Abstract: A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes means for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit includes a routing means for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.

Abstract: A nonvolatile memory system is described. The system includes ferroelectric memory cells each comprising a pair of metal plates and a ferroelectric material therebetween. Data are stored in the cells by applying an electric field corresponding to the desired data value across a given cell, thereby setting the polarity of the ferroelectric material to a given state. A datum is read from a cell by a mechanical force to the ferroelectric material and sensing charge induced on one of the cells.

Abstract: A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes means for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit includes a routing means for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.

Abstract: A nonvolatile memory system is described. The system includes ferroelectric memory cells each comprising a pair of metal plates and a ferroelectric material therebetween. Data are stored in the cells by applying an electric field corresponding to the desired data value across a given cell, thereby setting the polarity of the ferroelectric material to a given state. A datum is read from a cell by a mechanical force to the ferroelectric material and sensing charge induced on one of the cells.

Abstract: A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.

Abstract: A nonvolatile memory system is described. The system includes ferroelectric memory cells each comprising a pair of metal plates and a ferroelectric material therebetween. Data are stored in the cells by applying an electric field corresponding to the desired data value across a given cell, thereby setting the polarity of the ferroelectric material to a given state. A datum is read from a cell by a mechanical force to the ferroelectric material and sensing charge induced on one of the cells.

Abstract: A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes circuitry for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit includes a routing device for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.

Abstract: A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.

Abstract: A fully-connected nonblocking optical crossbar switch with minimal latency for interconnecting a plurality of sources to a plurality of destinations uses an array of photoemitters for each source and corresponding arrays of photodetectors that operate in a wavelength range for which silicon substrates are transparent. The crossbar switch includes a plurality of stacked silicon planes, each plane having an array of photdetectors occupying a unique location on its corresponding silicon plane so that no array of photodetectors blocks another array of photodetectors in the stacked silicon planes. The planes in the stack have varying lengths with a projecting edge of each plane having input/output pads for connecting electrical wiring to photodetectors of the plane. The stacked planes are arranged so that the input/output pads of each projecting edge are exposed for connection to an electrical bus. A plurality of light sources produce light signals representing data from the plurality of sources.

Abstract: A method for making a processor system immune to circuit failure caused by external noise using mirrored processors, and a recovery unit integral with the method, are disclosed. Identical addresses and data information is generated in each of two processors. The data is then partitioned into registers and Error Correction Codes (ECC's) are generated for the data. The address, data, and ECC information for each processor is then interlaced in a data structure. The interlaced structures of each processor are then compared. If the comparison yields no errors, the data is checkpointed in the recovery unit; if an error is detected, a recovery sequence can be initiated after the check-stop operation, whereby the system is restored to the last error-free checkpointing operation.