Patents by Inventor Ferenc Varadi

Ferenc Varadi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10288695
    Abstract: A method is described for ascertaining an internal resistance of an electrical energy accumulator. For this purpose, an analog voltage signal and an analog current signal are subjected to an analog to digital conversion and subsequently to band-pass filtering in order to obtain filtered voltage values and filtered current values. These are then checked with regard to different calculation prerequisites, whereupon a zero-phase resistance is calculated. Then, the calculated zero-phase resistance is supplied as internal resistance.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: May 14, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Robert Stolczenberger, Ferenc Varadi, Gabor Barany
  • Publication number: 20170254860
    Abstract: A method is described for ascertaining an internal resistance of an electrical energy accumulator. For this purpose, an analog voltage signal and an analog current signal are subjected to an analog to digital conversion and subsequently to band-pass filtering in order to obtain filtered voltage values and filtered current values. These are then checked with regard to different calculation prerequisites, whereupon a zero-phase resistance is calculated.
    Type: Application
    Filed: July 6, 2015
    Publication date: September 7, 2017
    Applicant: Robert Bosch GmbH
    Inventors: Robert Stolczenberger, Ferenc Varadi, Gabor Barany
  • Patent number: 9245071
    Abstract: A method for timing analysis of a circuit design includes, for each group of one or more instances of a cell of a cell library in the circuit design, determining timing related data for the group according to circuit context of the group in the design. The context includes at least one of a path depth, an output load, and an input slew rate. The determined timing related data are applied to analyze the circuit design.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: January 26, 2016
    Assignee: CLK DESIGN AUTOMATION, INC.
    Inventors: Isadore T. Katz, Joao M. Geada, Leon LaFrance, Ferenc Varadi, Ahran Dunsmoor, James Kuzeja, Shiva Raja
  • Publication number: 20130227510
    Abstract: A method for timing analysis of a circuit design includes, for each group of one or more instances of a cell of a cell library in the circuit design, determining timing related data for the group according to circuit context of the group in the design. The context includes at least one of a path depth, an output load, and an input slew rate. The determined timing related data are applied to analyze the circuit design.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Applicant: CIk Design Automation, Inc.
    Inventors: Isadore T. Katz, Joao M. Geada, Leon LaFrance, Ferenc Varadi, Ahran Dunsmoor, James Kuzeja, Shiva Raja