Patents by Inventor Fergus John Downey
Fergus John Downey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11841727Abstract: A reference generator system can include a PTAT circuit coupled to a signal supply node and configured to provide a voltage reference signal or a current reference signal that is based on a physical characteristic of one or more components of the PTAT circuit and a correction signal. The system can include a CTAT circuit coupled to the PTAT circuit and configured to provide the correction signal to the PTAT circuit. In an example, the reference generator system can be implemented at least in part using NMOS devices that comprise a portion of an indium gallium zinc oxide (IGZO) substrate.Type: GrantFiled: March 12, 2021Date of Patent: December 12, 2023Assignee: Analog Devices International Unlimited CompanyInventor: Fergus John Downey
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Publication number: 20230396265Abstract: The present disclosure relates to an integrated circuit with at least a first channel and a second channel. Each channel includes at least a DAC. The integrated circuit also includes a number of circuit elements interconnected between the channels. The circuit elements can be changed between a short circuit state and an open circuit state. Normally, each channel will operate independently of one another, using only the circuit components in its respective channel. However, the circuit elements are arranged to allow a user to combine part of the second channel with the first channel to improve the functionality and performance of the first channel. In particular, a state of the circuit elements can be chosen to combine components of the second channel with the first channel. For example, components (e.g. a sub-stage) of the second channel can be connected in parallel with corresponding components (e.g. a corresponding sub-stage) of the first channel.Type: ApplicationFiled: October 29, 2021Publication date: December 7, 2023Inventors: Fergus John Downey, Christian Steffen Birk, Dennis A. Dempsey, Ken Bryan Fulgosino Fabay
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Publication number: 20230396260Abstract: The present disclosure relates to a configurable output stage for a DAC channel. The output stage receives an analog output from a DAC and outputs a signal to an output terminal. The output stage is configurable between a voltage mode and a current mode. In the voltage mode, the output stage supplies the analog signal to the output terminal as a voltage signal. In the current mode, the output stage supplies the analog signal to the output signal as a current signal. The output stage can receive user input to select the desired mode. Consequently, an integrated circuit can be implemented with multiple DAC channels, each having the configurable output stage. A user can choose how many channels they want to operate in a voltage output mode, and how many channels they want to operate in a current output mode, depending on their individual requirements.Type: ApplicationFiled: October 29, 2021Publication date: December 7, 2023Inventors: Dennis A. Dempsey, Michael C. Lynch, Ivan Bucoy Santos, Fintan M. Leamy, Fergus John Downey
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Patent number: 11256652Abstract: A Multi-I/O SPI for precision converters supports a Dual/Quad/Octal SPI to support the speed requirements for digital transmission and also includes a special mode that can be enabled by hardware and/or software to remove the bit scrambling requirement dictated by the JEDEC standard. The special mode removes the scramble requirement and associates each of the bidirectional data lines to a specific channel. The special mode provides backward compatibility that permits the precision converter to be used with controllers that do not natively support the JEDEC standard. Also, the Multi-I/O SPI includes registers divided into a primary region that is accessed only in default mode at power-up for write and/or read operations, and a secondary region that is accessed by any mode enabled in the control register. By restricting access to the “control” register area to a pre-defined mode in the converter at power-up, the access mode can be controlled.Type: GrantFiled: May 20, 2020Date of Patent: February 22, 2022Assignee: Analog Devices International Unlimited CompanyInventors: Miguel Usach Merino, Wes Vernon Lofamia, Fergus John Downey, David A. Browne, Thomas Murphy
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Publication number: 20210286395Abstract: A reference generator system can include a PTAT circuit coupled to a signal supply node and configured to provide a voltage reference signal or a current reference signal that is based on a physical characteristic of one or more components of the PTAT circuit and a correction signal. The system can include a CTAT circuit coupled to the PTAT circuit and configured to provide the correction signal to the PTAT circuit. In an example, the reference generator system can be implemented at least in part using NMOS devices that comprise a portion of an indium gallium zinc oxide (IGZO) substrate.Type: ApplicationFiled: March 12, 2021Publication date: September 16, 2021Inventor: Fergus John Downey
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Publication number: 20200401549Abstract: A Multi-I/O SPI for precision converters supports a Dual/Quad/Octal SPI to support the speed requirements for digital transmission and also includes a special mode that can be enabled by hardware and/or software to remove the bit scrambling requirement dictated by the JEDEC standard. The special mode removes the scramble requirement and associates each of the bidirectional data lines to a specific channel. The special mode provides backward compatibility that permits the precision converter to be used with controllers that do not natively support the JEDEC standard. Also, the Multi-I/O SPI includes registers divided into a primary region that is accessed only in default mode at power-up for write and/or read operations, and a secondary region that is accessed by any mode enabled in the control register. By restricting access to the “control” register area to a pre-defined mode in the converter at power-up, the access mode can be controlled.Type: ApplicationFiled: May 20, 2020Publication date: December 24, 2020Inventors: Miguel Usach Merino, Wes Vernon Lofamia, Fergus John Downey, David A. Browne, Thomas Murphy
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Patent number: 10615817Abstract: Digital to analog converter architectures are disclosed that enable the binary scaling of transistor sized to be replaced by transistors of substantially the same size. This significantly reduced the size of the Digital to Analog converter on a wafer. As the currents from the lesser bits of the converter may be very small indeed, some of the transistors are operated in a regime where the gate-source voltage applied to the transistor is below the threshold voltage for the device, the threshold voltage generally being regarded as marking the onset of significant conduction through a field effect transistor.Type: GrantFiled: February 13, 2018Date of Patent: April 7, 2020Assignee: Analog Devices Global Unlimited CompanyInventor: Fergus John Downey
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Publication number: 20190140656Abstract: Digital to analog converter architectures are disclosed that enable the binary scaling of transistor sized to be replaced by transistors of substantially the same size. This significantly reduced the size of the Digital to Analog converter on a wafer. As the currents from the lesser bits of the converter may be very small indeed, some of the transistors are operated in a regime where the gate-source voltage applied to the transistor is below the threshold voltage for the device, the threshold voltage generally being regarded as marking the onset of significant conduction through a field effect transistor.Type: ApplicationFiled: February 13, 2018Publication date: May 9, 2019Inventor: Fergus John Downey
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Patent number: 9136866Abstract: A digital-to-analog converter (DAC) comprising a first section having a first plurality of current flow paths forming binary weighted values in the DAC; and a second section connected to the first section and having a second plurality of current flow paths, wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are notionally equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section.Type: GrantFiled: October 9, 2013Date of Patent: September 15, 2015Assignee: ANALOG DEVICES GLOBALInventors: Fergus John Downey, Roderick McLachlan
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Publication number: 20150097712Abstract: A digital-to-analog converter (DAC) comprising a first section having a first plurality of current flow paths forming binary weighted values in the DAC; and a second section connected to the first section and having a second plurality of current flow paths, wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are notionally equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section.Type: ApplicationFiled: October 9, 2013Publication date: April 9, 2015Applicant: Analog Devices TechnologyInventors: Fergus John DOWNEY, Roderick McLACHLAN
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Patent number: 8723637Abstract: A method for altering a resistance of a resistor including trimming the resistor using a first type of trim approach to increase a resistance measurement of the resistor to above a target resistance value, and iteratively trimming the resistor using a second type of trim approach until a power coefficient of resistance (PCR) or temperature coefficient of resistance (TCR) measurement of the resistor is substantially close to zero.Type: GrantFiled: July 20, 2012Date of Patent: May 13, 2014Assignee: Analog Devices, Inc.Inventors: Fergus John Downey, Neville Craig, Patrick McGuinness, Patrick Elebert
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Publication number: 20130265133Abstract: A method for altering a resistance of a resistor including trimming the resistor using a first type of trim approach to increase a resistance measurement of the resistor to above a target resistance value, and iteratively trimming the resistor using a second type of trim approach until a power coefficient of resistance (PCR) or temperature coefficient of resistance (TCR) measurement of the resistor is substantially close to zero.Type: ApplicationFiled: July 20, 2012Publication date: October 10, 2013Applicant: ANALOG DEVICES, INC.Inventors: Fergus John Downey, Neville Craig, Patrick McGuiness, Patrick Elebert
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Patent number: 8441335Abstract: Apparatus and methods of trimming resistors are disclosed. In one embodiment, a method of controlling the PCR of a thin film resistor is provided. The method includes applying a first current to a resistor so as to alter a property of the resistor, and measuring the property of the resistor. Applying the first current and measuring the property of the resistor can be repeated until the PCR of the resistor is within an acceptable tolerance of a desired value for the property of the resistor.Type: GrantFiled: October 21, 2010Date of Patent: May 14, 2013Assignee: Analog Devices, Inc.Inventors: Fergus John Downey, Bernard Patrick Stenson, James Michael Molyneaux
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Publication number: 20120098593Abstract: Apparatus and methods of trimming resistors are disclosed. In one embodiment, a method of controlling the PCR of a thin film resistor is provided. The method includes applying a first current to a resistor so as to alter a property of the resistor, and measuring the property of the resistor. Applying the first current and measuring the property of the resistor can be repeated until the PCR of the resistor is within an acceptable tolerance of a desired value for the property of the resistor.Type: ApplicationFiled: October 21, 2010Publication date: April 26, 2012Applicant: ANALOG DEVICES, INC.Inventors: Fergus John Downey, Bernard Patrick Stenson, James Michael Molyneaux