Abstract: A ring interconnect system comprises a plurality of nodes. Each node is connected to two other nodes to form a ring interconnect. Every pair of nodes is connected by an inter-node path for that pair of nodes distinct from the ring interconnect. Each of the nodes comprises a message buffer to buffer messages received from at least one device associated with the node. Each of the nodes also comprises activity level circuitry to transmit an activity indication, when a number of the messages in the message buffer is equal to or above a threshold, to each other node of the plurality of nodes via the respective inter-node paths. Each of the nodes also comprises arbitrator circuitry to receive the activity indications from each other node and from the activity level circuitry, and to allow ingress of a message from the message buffer onto the ring interconnect in dependence on the activity indications. Also provided is a method of operating a node of a ring interconnect system.

Abstract: An interconnect apparatus comprises first node circuitry for performing first node operations to service data access requests in respect of a first range of memory addresses and second node circuitry for performing second node operations to service data access requests in respect of a second range of memory addresses. The interconnect comprises interface circuitry to: receive a retry indication in respect of a data access request from the first node and forward the retry indication to the requester circuitry; responsive to determining that the interface circuitry has capacity for the data access request, transmit a reissue capacity message to the requester circuitry; receive a reissued data access request from the requester circuitry; and issue the reissued data access request to the second node circuitry. The second node circuitry is responsive to receiving the reissued data access request to service the data access request.

Abstract: An interconnect apparatus comprises first node circuitry for performing first node operations to service data access requests in respect of a first range of memory addresses and second node circuitry for performing second node operations to service data access requests in respect of a second range of memory addresses. The interconnect comprises interface circuitry to: receive a retry indication in respect of a data access request from the first node and forward the retry indication to the requester circuitry; responsive to determining that the interface circuitry has capacity for the data access request, transmit a reissue capacity message to the requester circuitry; receive a reissued data access request from the requester circuitry; and issue the reissued data access request to the second node circuitry. The second node circuitry is responsive to receiving the reissued data access request to service the data access request.

Abstract: There is provided an apparatus comprising scheduling circuitry, which selects a task as a selected task to be performed from a plurality of queued tasks, each having an associated priority, in dependence on the associated priority of each queued task. Escalating circuitry increases the associated priority of each of the plurality of queued tasks after a period of time. The plurality of queued tasks comprises a time-sensitive task having an associated deadline and in response to the associated deadline being reached, the scheduling circuitry selects the time-sensitive task as the selected task to be performed.

Abstract: A first event source generates a first indication of a first event which has occurred in the first event source, the first indication being one of a predefined set of indications corresponding to a plurality of event types. A second event source generates a second indication of a second event which has occurred in the second event source, the second indication being one of the predefined set of indications corresponding to the plurality of event types. First event selection circuitry responds to the first indication matching a selected event type of the plurality of event types to generate a first count signal and second event selection circuitry responds to the second indication matching the selected event type of the plurality of event types to generate a second count signal. Count circuitry increments a counter in response to either the first count signal or the second count signal.

Abstract: A ring interconnect system comprises a plurality of nodes. Each node is connected to two other nodes to form a ring interconnect. Every pair of nodes is connected by an inter-node path for that pair of nodes distinct from the ring interconnect. Each of the nodes comprises a message buffer to buffer messages received from at least one device associated with the node. Each of the nodes also comprises activity level circuitry to transmit an activity indication, when a number of the messages in the message buffer is equal to or above a threshold, to each other node of the plurality of nodes via the respective inter-node paths. Each of the nodes also comprises arbitrator circuitry to receive the activity indications from each other node and from the activity level circuitry, and to allow ingress of a message from the message buffer onto the ring interconnect in dependence on the activity indications.

Abstract: A first event source generates a first indication of a first event which has occurred in the first event source, the first indication being one of a predefined set of indications corresponding to a plurality of event types. A second event source generates a second indication of a second event which has occurred in the second event source, the second indication being one of the predefined set of indications corresponding to the plurality of event types. First event selection circuitry responds to the first indication matching a selected event type of the plurality of event types to generate a first count signal and second event selection circuitry responds to the second indication matching the selected event type of the plurality of event types to generate a second count signal. Count circuitry increments a counter in response to either the first count signal or the second count signal.

Abstract: A technique is described for performing a maintenance operation within an apparatus that is used to control access to a memory device. The apparatus has a storage device for storing access requests to be issued to the memory device, and maintenance circuitry for performing a maintenance operation on storage elements provided within the storage device. Memory access execution circuitry is used to issue to a physical layer interface access requests selected from the storage device, for onward propagation from the physical layer interface to the memory device. Control circuitry is responsive to a training event to initiate a training operation of the physical layer interface. In addition, the control circuitry is further responsive to the training event to trigger performance of the maintenance operation by the maintenance circuitry whilst the training operation is being performed.

Abstract: A technique is described for performing a maintenance operation within an apparatus that is used to control access to a memory device. The apparatus has a storage device for storing access requests to be issued to the memory device, and maintenance circuitry for performing a maintenance operation on storage elements provided within the storage device. Memory access execution circuitry is used to issue to a physical layer interface access requests selected from the storage device, for onward propagation from the physical layer interface to the memory device. Control circuitry is responsive to a training event to initiate a training operation of the physical layer interface. In addition, the control circuitry is further responsive to the training event to trigger performance of the maintenance operation by the maintenance circuitry whilst the training operation is being performed.

Abstract: There is provided an apparatus comprising scheduling circuitry, which selects a task as a selected task to be performed from a plurality of queued tasks, each having an associated priority, in dependence on the associated priority of each queued task. Escalating circuitry increases the associated priority of each of the plurality of queued tasks after a period of time. The plurality of queued tasks comprises a time-sensitive task having an associated deadline and in response to the associated deadline being reached, the scheduling circuitry selects the time-sensitive task as the selected task to be performed.