Abstract: A deployment server can include a profile data store, a generic application data store, and an optimizer. The profile data store can contain a plurality of attributes for devices and associate different optimization parameters or optimization routines to each of the stored attributes. The generic application data store can contain at least one generic application written in a device independent fashion. The optimizer can receive application requests from an assortment of different requesting devices and can dynamically generate device-specific applications responsive to received requests. For each requesting device, the optimizer can determine attributes of a requesting device, utilize the profile data store to identify optimization parameters or optimization routines for the requesting device, and generate a device-specific application based upon data from the profile data store and based upon a generic application retrieved from the generic application data store.

Abstract: A deployment server can include a profile data store, a generic application data store, and an optimizer. The profile data store can contain a plurality of attributes for devices and associate different optimization parameters or optimization routines to each of the stored attributes. The generic application data store can contain at least one generic application written in a device independent fashion. The optimizer can receive application requests from an assortment of different requesting devices and can dynamically generate device-specific applications responsive to received requests. For each requesting device, the optimizer can determine attributes of a requesting device, utilize the profile data store to identify optimization parameters or optimization routines for the requesting device, and generate a device-specific application based upon data from the profile data store and based upon a generic application retrieved from the generic application data store.

Abstract: To provide for efficient use of computer microcodes, a firmware structure containing a mainline programmable logic array circuit and at least one subroutine programmable logic array circuit may be used. As the states of the mainline programmable logic array circuit are sequenced, the data bits representing the encode number field in its OR array are compared with the data bits representing the encode number field of the AND array of the subroutine programmable logic array circuit. If a match is made, the mainline programmable logic array circuit suspends its operation and sequencing of the subroutine programmable logic array circuit begins, in order to perform the function required. Upon completion of the function, control is automatically transferred from the subroutine programmable logic array circuit back to the mainline programmable logic array circuit, at the point where it was suspended.

Abstract: Error detection and correction logic is interposed between a 16-bit CPU and a data storage unit with a 32-bit word size and single bit error correction and double bit error detection (ECC) code bits. During each CPU Read cycle, a full word and its ECC bits are read from storage; and a selected 16 data bits are transferred to the CPU directly if they are error free or are corrected by the ECC logic and then transferred if they have only one bit with an error. During each CPU Write cycle, a selected full word and its ECC bits are read from storage; 16 data bits of the word are replaced by 16 data bits from the CPU; ECC bits are calculated for the modified word; and the modified word and its ECC bits are entered into the storage unit so long as no error exists in the remaining 16 bits of the data word which were not replaced/modified. This type of operation is often referred to as a Read-Modify-Write (RMW) cycle.