Abstract: The present invention relates to reading-out sensor array pixels. In particular, the present invention provides an approach according to which only a region of interest is may be read out from the sensor array, thus leading to substantial time savings. In order to achieve this, a circuitry for configuring a region of interest for the sensor array is provided as well as a reading-out circuitry for reading-out pixels belonging to the region of interest. In addition, the corresponding methods for programming the region of interest and for reading-out the region of interest are provided. The circuitry for programming and/or reading-out the region of interest includes per pixel provided storage elements for storing an indication of whether a pixel belongs to a region of interest (ROI). These are configured by the programming circuitry and using when reading-out the ROI for only reading out the pixels of the ROI.

Abstract: The present invention relates to reading-out sensor array pixels. In particular, the present invention provides an approach according to which only a region of interest with arbitrary geometry may be read out from the sensor array, thus leading to substantial time savings. In order to achieve this, a circuitry is provided for automatic determining of a ROI and reading out the ROI from the sensor array. The circuitry includes a fast reading-out circuitry which is less precise but faster than the accurate reading-out circuitry for reading-out the pixels of the sensor array. The fast reading-out circuitry reads out the pixels with low-level precision and determines by the processing of the fast read-out pixels the ROI which is then provided to an in-pixel ROI programming circuit for storing the ROI identification and by means thereof to the accurate reading-out circuit which then reads out only the pixels determined to belong to the ROI. The accurate read-out circuit is slower than the fast read-out circuit.

Abstract: The present invention relates to a two- or multiple-stage analog to digital converter. The converter preferably includes an incremental ADC in the first stage. The incremental ADC comprises an integrator and a comparator. After the predefined number of comparisons performed by the comparator, the output of the integrator appropriately scaled is provided to the second stage where it is further sampled. In particular, the scaling gain is inversely proportional to the integrator gain. The second ADC performs the conversion of the remaining least significant bits and then the output of both stages is combined. Moreover, a calibration and correction approaches are provided for the multi-stage ADC.

Abstract: The present invention relates to reading-out sensor array pixels. In particular, the present invention provides an approach according to which only a region of interest with arbitrary geometry may be read out from the sensor array, thus leading to substantial time savings. In order to achieve this, a circuitry is provided for automatic determining of a ROI and reading out the ROI from the sensor array. The circuitry includes a fast reading-out circuitry which is less precise but faster than the accurate reading-out circuitry for reading-out the pixels of the sensor array. The fast reading-out circuitry reads out the pixels with low-level precision and determines by the processing of the fast read-out pixels the ROI which is then provided to an in-pixel ROI programming circuit for storing the ROI identification and by means thereof to the accurate reading-out circuit which then reads out only the pixels determined to belong to the ROI. The accurate read-out circuit is slower than the fast read-out circuit.

Abstract: The present invention relates to reading-out sensor array pixels. In particular, the present invention provides an approach according to which only a region of interest is may be read out from the sensor array, thus leading to substantial time savings. In order to achieve this, a circuitry for configuring a region of interest for the sensor array is provided as well as a reading-out circuitry for reading-out pixels belonging to the region of interest. In addition, the corresponding methods for programming the region of interest and for reading-out the region of interest are provided. The circuitry for programming and/or reading-out the region of interest includes per pixel provided storage elements for storing an indication of whether a pixel belongs to a region of interest (ROI). These are configured by the programming circuitry and using when reading-out the ROI for only reading out the pixels of the ROI.

Abstract: The present invention relates to a two- or multiple-stage analog to digital converter. The converter preferably includes an incremental ADC in the first stage. The incremental ADC comprises an integrator and a comparator. After the predefined number of comparisons performed by the comparator, the output of the integrator appropriately scaled is provided to the second stage where it is further sampled. In particular, the scaling gain is inversely proportional to the integrator gain. The second ADC performs the conversion of the remaining least significant bits and then the output of both stages is combined. Moreover, a calibration and correction approaches are provided for the multi-stage ADC.

Abstract: The objective of this invention is to provide a solid-state image pickup device and its driving method that has a minimum circuit area and a wide dynamic range. The invention includes: a sensor array SA; a memory M; and a signal determination circuit DC. The sensor array has plural pixels in an array integrated on a semiconductor substrate. Each pixel sequentially outputs a first signal and a second signal. The memory M is connected to each column of pixels array and stores the first signal or the second signal. The signal determination circuit DC outputs signal (SS) such that it works as follows: when the first signal is input to memory M from the pixel, the signal determination circuit DC determines whether the first signal can be used. If so, the first signal is selected and the second signal is discarded and is not output to memory M. When the second signal is selected, the second signal is uploaded to memory M.

Abstract: This invention is an amplification circuit which limits increased power consumption and circuit surface area use and an imaging device including this amplification circuit. After initially discharging a capacitor, a signal charge corresponding to the difference between pixel signals is transferred repeatedly to the capacitor during an integration phase storing a signal charge proportional to the number of repetitions. The output of amplification is the signal charge accumulated in the capacitor. The gain is independent of the capacitor capacitance ratio. Thus the capacitor size can be smaller than conventional amplification circuits.

Abstract: This invention is an image pickup device that realizes a wide dynamic range while minimizing circuit area using a pixel array that can pick up a low-sensitivity image and a high-sensitivity image. This invention obtains information (S1/S2) needed for generating a correction coefficient using one more than the number of pixels readout circuits (RC1 to RCn+1). This significantly reduces the circuit area compared with the case of using twice as many readout circuits as pixels for generating the correction coefficient.

Abstract: This invention is an image pickup device that realizes a wide dynamic range while minimizing circuit area using a pixel array that can pick up a low-sensitivity image and a high-sensitivity image. This invention obtains information (S1/S2) needed for generating a correction coefficient using one more than the number of pixels readout circuits (RC1 to RCn+1). This significantly reduces the circuit area compared with the case of using twice as many readout circuits as pixels for generating the correction coefficient.

Abstract: The objective of this invention is to provide a solid-state image pickup device and its driving method that has a minimum circuit area and a wide dynamic range. The invention includes: a sensor array SA; a memory M; and a signal determination circuit DC. The sensor array has plural pixels in an array integrated on a semiconductor substrate. Each pixel sequentially outputs a first signal and a second signal. The memory M is connected to each column of pixels array and stores the first signal or the second signal. The signal determination circuit DC outputs signal (SS) such that it works as follows: when the first signal is input to memory M from the pixel, the signal determination circuit DC determines whether the first signal can be used. If so, the first signal is selected and the second signal is discarded and is not output to memory M. When the second signal is selected, the second signal is uploaded to memory M.

Abstract: This invention is an amplification circuit which limits increased power consumption and circuit surface area use and an imaging device including this amplification circuit. After initially discharging a capacitor, a signal charge corresponding to the difference between pixel signals is transferred repeatedly to the capacitor during an integration phase storing a signal charge proportional to the number of repetitions. The output of amplification is the signal charge accumulated in the capacitor. The gain is independent of the capacitor capacitance ratio. Thus the capacitor size can be smaller than conventional amplification circuits.