Patents by Inventor Fifin Sweeney
Fifin Sweeney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9349692Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.Type: GrantFiled: May 4, 2015Date of Patent: May 24, 2016Assignee: QUALCOMM IncorporatedInventors: Yuan-cheng Christopher Pan, Fifin Sweeney, Lew Go Chua-Eoan, Zhi Zhu, Junmou Zhang, Jason Gonzalez
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Publication number: 20150235952Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.Type: ApplicationFiled: May 4, 2015Publication date: August 20, 2015Inventors: Yuancheng Christopher Pan, Fifin Sweeney, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang
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Patent number: 9048112Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.Type: GrantFiled: June 29, 2010Date of Patent: June 2, 2015Assignee: QUALCOMM IncorporatedInventors: Yuancheng Christopher Pan, Fifin Sweeney, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang
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Patent number: 8847375Abstract: An integrated circuit package includes a microelectromechanical systems (MEMS) device embedded in a packaging substrate. The MEMS device is located on a die embedded in the packaging substrate and covered by a hermetic seal. Low-stress material in the packaging substrate surrounds the MEMS device. Additionally, interconnects may be used as standoffs to reduce stress on the MEMS device. The MEMS device is embedded a distance into the packaging substrate leaving for example, 30-80 microns, between the hermetic seal of the MEMS device and the support surface of the packaging substrate. Embedding the MEMS device results in lower stress on the MEMS device.Type: GrantFiled: January 28, 2010Date of Patent: September 30, 2014Assignee: QUALCOMM IncorporatedInventors: Milind P. Shah, Mario Francisco Velez, Fifin Sweeney
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Patent number: 8633597Abstract: In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.Type: GrantFiled: March 1, 2010Date of Patent: January 21, 2014Assignee: QUALCOMM IncorporatedInventors: Fifin Sweeney, Milind P. Shah, Mario Francisco Velez, Damion B. Gastelum
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Publication number: 20130270718Abstract: A package includes a printed circuit board (PCB) having a first side and a second side and a thickness between the first side and the second side and a stacked die including a top die mounted on a bottom die, the bottom die being at least partially embedded in the PCB. Also a method of forming a package that includes forming an opening in a top surface of the PCB layer, placing a stacked die including a top die stacked on a bottom die into the opening, laminating the PCB layer to form a laminate layer, and forming an electrical connection with the stacked die.Type: ApplicationFiled: June 17, 2013Publication date: October 17, 2013Inventors: Fifin Sweeney, Jason R. Gonzalez
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Patent number: 8476750Abstract: A package includes a printed circuit board (PCB) having a first side and a second side and a thickness between the first side and the second side and a stacked die including a top die mounted on a bottom die, the bottom die being at least partially embedded in the PCB. Also a method of forming a package that includes forming an opening in a top surface of the PCB layer, placing a stacked die including a top die stacked on a bottom die into the opening, laminating the PCB layer to form a laminate layer, and forming an electrical connection with the stacked die.Type: GrantFiled: December 10, 2009Date of Patent: July 2, 2013Assignee: QUALCOMM IncorporatedInventors: Fifin Sweeney, Jason R. Gonzalez
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Publication number: 20110317387Abstract: A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.Type: ApplicationFiled: June 29, 2010Publication date: December 29, 2011Applicant: QUALCOMM IncorporatedInventors: Yuancheng Christopher Pan, Fifin Sweeney, Lew G. Chua-Eoan, Zhi Zhu, Junmou Zhang
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Publication number: 20110210438Abstract: In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.Type: ApplicationFiled: March 1, 2010Publication date: September 1, 2011Applicant: QUALCOMM IncorporatedInventors: Fifin Sweeney, Milind P. Shah, Mario Francisco Velez, Damion B. Gastelum
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Publication number: 20110180926Abstract: An integrated circuit package includes a microelectromechanical systems (MEMS) device embedded in a packaging substrate. The MEMS device is located on a die embedded in the packaging substrate and covered by a hermetic seal. Low-stress material in the packaging substrate surrounds the MEMS device. Additionally, interconnects may be used as standoffs to reduce stress on the MEMS device. The MEMS device is embedded a distance into the packaging substrate leaving for example, 30-80 microns, between the hermetic seal of the MEMS device and the support surface of the packaging substrate. Embedding the MEMS device results in lower stress on the MEMS device.Type: ApplicationFiled: January 28, 2010Publication date: July 28, 2011Applicant: QUALCOMM INCORPORATEDInventors: Milind P. Shah, Mario Francisco Velez, Fifin Sweeney
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Publication number: 20110140257Abstract: A package includes a printed circuit board (PCB) having a first side and a second side and a thickness between the first side and the second side and a stacked die including a top die mounted on a bottom die, the bottom die being at least partially embedded in the PCB. Also a method of forming a package that includes forming an opening in a top surface of the PCB layer, placing a stacked die including a top die stacked on a bottom die into the opening, laminating the PCB layer to form a laminate layer, and forming an electrical connection with the stacked die.Type: ApplicationFiled: December 10, 2009Publication date: June 16, 2011Applicant: QUALCOMM IncorporatedInventors: Fifin Sweeney, Jason R. Gonzalez
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Publication number: 20100327433Abstract: An integrated circuit package includes a decoupling capacitor. The integrated circuit package also includes a packaging substrate. The decoupling capacitor is at least partially embedded in the packaging substrate. The integrated circuit package further includes a die mounted to the packaging substrate. The die is coupled to the decoupling capacitor. The die receiving substantially instantaneous current from the decoupling capacitor.Type: ApplicationFiled: June 25, 2009Publication date: December 30, 2010Applicant: QUALCOMM INCORPORATEDInventors: Fifin Sweeney, Mario Francisco Velez, Yuancheng Christopher Pan, Shiqun Gu
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Publication number: 20100155931Abstract: An integrated circuit package has a die or die stack with through silicon vias embedded in a package substrate. A method of producing an integrated circuit package embeds at least one die with a through silicon via in a package substrate. The package substrate provides a protective cover for the die or die stack.Type: ApplicationFiled: December 22, 2008Publication date: June 24, 2010Applicant: QUALCOMM INCORPORATEDInventors: Urmi Ray, Fifin Sweeney, Kenneth Kaskoun, Shiquin Gu, Thomas R. Toms
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Publication number: 20100123215Abstract: A semiconductor package has a capacitor die and a packaging substrate. The capacitor die is coupled to circuitry on a front or back side of a die coupled to the packaging substrate for providing decoupling capacitance. In one example, the capacitor die is coupled to a land side of the packaging substrate in an area depopulated of a packaging array and adjacent to the packaging array. In another example, the capacitor die may be stacked on the die and coupled through wire bonds to circuitry on the die. The capacitor die reduces impedance of the integrated circuit allowing operation at higher frequencies.Type: ApplicationFiled: November 18, 2009Publication date: May 20, 2010Applicant: QUALCOMM INCORPORATEDInventors: Yuancheng Christopher Pan, Fifin Sweeney, Charlie Paynter, Kevin R. Bowles, Jason R. Gonzalez