Abstract: A data processing apparatus and method for transmitting data in a data processing apparatus are provided. A data processing apparatus provided has a data input for receiving data, a processor for processing the data with an input, a data supply suppression unit which is connected between the data input and the input and suppresses or permits supply of the data from the data input to the input, and a control unit coupled to the data supply suppression unit for producing a control signal. The control signal represents at least one operating condition or a quiescent condition for the processor. The data supply suppression unit is suitable for suppressing or permitting supply of the data from the data input to the input. It is set up such that it suppresses supply of the data from the data input to the input when the control signal represents a quiescent condition for the processor.

Abstract: A data processing apparatus and method for transmitting data in a data processing apparatus are provided. A data processing apparatus provided has a data input for receiving data, a processor for processing the data with an input, a data supply suppression unit which is connected between the data input and the input and suppresses or permits supply of the data from the data input to the input, and a control unit coupled to the data supply suppression unit for producing a control signal. The control signal represents at least one operating condition or a quiescent condition for the processor. The data supply suppression unit is suitable for suppressing or permitting supply of the data from the data input to the input. It is set up such that it suppresses supply of the data from the data input to the input when the control signal represents a quiescent condition for the processor.

Abstract: An addition circuit for digital data includes a digital adder for the addition of digital input data values present at data inputs of the digital adder to form a summation output data value, at an output of the digital adder. The data inputs have a predetermined data bit width n. A saturation circuit for limits the summation output data value present at a data input of the saturation circuit to be within a range determined by an upper threshold data value and a lower threshold data value. The n?m least significant data bits of the summation output data value are present directly at the data input of the saturation circuit, whereas the m most significant data bits of the summation output data value are switched through to the data input of the saturation circuit via a clock-state-controlled latch register.

Abstract: In a method for variable weighting of channel coefficients for a RAKE receiver, at least one variable that is characteristic of a transmitter and/or transmission channel and/or receiver characteristic is assessed. A correction factor is determined, which is dependent on the assessment result. The channel coefficients are multiplied by the correction factor, and the corrected channel coefficients are used as the basis for equalization in the RAKE receiver.

Abstract: An addition circuit for digital data includes a digital adder for the addition of digital input data values present at data inputs of the digital adder to form a summation output data value, at an output of the digital adder. The data inputs have a predetermined data bit width n. A saturation circuit for limits the summation output data value present at a data input of the saturation circuit to be within a range determined by an upper threshold data value and a lower threshold data value. The n-m least significant data bits of the summation output data value are present directly at the data input of the saturation circuit, whereas the m most significant data bits of the summation output data value are switched through to the data input of the saturation circuit via a clock-state-controlled latch register.