Abstract: In one embodiment, the present invention includes an electronic circuit comprising a first stage having a first differential inductive element and a second differential inductive element, and a second stage coupled to an output of the first stage, the second stage having a first differential inductive element and a second differential inductive element, wherein the first and second differential inductive elements of the first stage couple magnetically to generate a first phase error, wherein the first and second differential inductive elements of the second stage couple magnetically to generate a second phase error, and wherein the second phase error cancels the first phase error.

Abstract: In one embodiment, the present invention includes an electronic circuit comprising a first stage having a first differential inductive element and a second differential inductive element, and a second stage coupled to an output of the first stage, the second stage having a first differential inductive element and a second differential inductive element, wherein the first and second differential inductive elements of the first stage couple magnetically to generate a first phase error, wherein the first and second differential inductive elements of the second stage couple magnetically to generate a second phase error, and wherein the second phase error cancels the first phase error.

Abstract: A vertical gate-depleted single electron transistor (SET) is fabricated on a conducting or insulating substrate. A plurality of lightly doped basic materials and tunneling barriers are fabricated on top of a substrate, wherein at least two of the layers of basic materials sandwich the layers of tunneling barriers and at least two of the layers of tunneling barriers sandwich at least one of the layers of basic materials. A mesa is fabricated on top of the layers of basic materials and tunneling barriers, and has an undercut shape. An ohmic contact is fabricated on top of the mesa, and one or more gate Schottky contacts are fabricated on top of the layers of lightly doped basic materials and tunneling barriers. A quantum dot is induced by gate depletion, when a source voltage is set as zero, a drain voltage is set to be less than 0.1, and a gate voltage is set to be negative.

Abstract: A vertical gate-depleted single electron transistor (SET) is fabricated on a conducting or insulating substrate. A plurality of lightly doped basic materials and tunneling barriers are fabricated on top of a substrate, wherein at least two of the layers of basic materials sandwich the layers of tunneling barriers and at least two of the layers of tunneling barriers sandwich at least one of the layers of basic materials. A mesa is fabricated on top of the layers of basic materials and tunneling barriers, and has an undercut shape. An ohmic contact is fabricated on top of the mesa, and one or more gate Schottky contacts are fabricated on top of the layers of lightly doped basic materials and tunneling barriers. A quantum dot is induced by gate depletion, when a source voltage is set as zero, a drain voltage is set to be less than 0.1, and a gate voltage is set to be negative.

Abstract: Embodiments of the present invention include a frequency synthesizer comprising a first plurality of dividers receiving a first signal having a first frequency and generating a first plurality of divided signals and a frequency combination network including a plurality of mixers, the frequency combination network receiving one or more of the first plurality of divided signals and generating a plurality of synthesized signals having different frequencies. The frequency combination network may further include additional dividers and multiplexers for more flexibility in synthesizing different frequencies. In one embodiment, the frequency combination network is coupled to dividers in the feedback path of a phase locked loop. The present invention is particularly advantageous for synthesizing frequencies above one (1) gigahertz.

Abstract: Embodiments of the present invention include a frequency synthesizer comprising a first plurality of dividers receiving a first signal having a first frequency and generating a first plurality of divided signals and a frequency combination network including a plurality of mixers, the frequency combination network receiving one or more of the first plurality of divided signals and generating a plurality of synthesized signals having different frequencies. The frequency combination network may further include additional dividers and multiplexers for more flexibility in synthesizing different frequencies. In one embodiment, the frequency combination network is coupled to dividers in the feedback path of a phase locked loop. The present invention is particularly advantageous for synthesizing frequencies above one (1) gigahertz.