Patents by Inventor Filippo Marino
Filippo Marino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11671006Abstract: In an example, a system comprises a boost power factor correction (PFC) converter that includes a thermistor, an inductor, and a transistor and a PFC controller coupled to a common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a terminal of the transistor. A first flip-flop is coupled to the comparator and to a control terminal of the transistor. A zero current detector is coupled to the inductor. A timer is coupled to the comparator and to the zero current detector. A second flip-flop is coupled to the timer and to the control terminal of the transistor. An AND gate is coupled to the first and second flip-flops. The circuit includes third and fourth flip flops.Type: GrantFiled: April 16, 2021Date of Patent: June 6, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joseph Michael Leisten, Salvatore Giombanco, Filippo Marino, Rosario Davide Stracquadaini
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Publication number: 20210279623Abstract: Determination of a user-specific likelihood of incident occurrence at a geographic location may be performed. User information, historical incident information, contextual information, and/or other information may be obtained. User information may include user demographic information, user behavior information, user social information, and/or other user related information. Historical incident information may include data relating to crime, mortality, injury, morbidity rates and may be obtained from local law enforcement, local Departments of Motor Vehicles, national security agency, foreign security agency, international criminal policy organization, national public health agency, international public health agency and/or other sources. Contextual information may include information about events that have previously occurred at or near user's current geographic location.Type: ApplicationFiled: May 21, 2021Publication date: September 9, 2021Inventor: Filippo Marino
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Publication number: 20210234458Abstract: In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.Type: ApplicationFiled: April 16, 2021Publication date: July 29, 2021Inventors: Joseph Michael LEISTEN, Salvatore GIOMBANCO, Filippo MARINO, Rosario Davide STRACQUADAINI
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Patent number: 11030543Abstract: Determination of a user-specific likelihood of incident occurrence at a geographic location may be performed. User information, historical incident information, contextual information, and/or other information may be obtained. User information may include user demographic information, user behavior information, user social information, and/or other user related information. Historical incident information may include data relating to crime, mortality, injury, morbidity rates and may be obtained from local law enforcement, local Departments of Motor Vehicles, national security agency such as the Federal Bureau of Investigation, foreign security agency such as the Central Intelligence Agency, international criminal policy organization such as Interpol, national public health agency such as Center for Disease Control, international public health agency such as World Health Organization and/or other sources.Type: GrantFiled: August 14, 2017Date of Patent: June 8, 2021Assignee: Safe-esteem, IncInventor: Filippo Marino
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Patent number: 11011975Abstract: In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.Type: GrantFiled: December 14, 2018Date of Patent: May 18, 2021Assignee: Texas Instruments IncorporatedInventors: Joseph Michael Leisten, Salvatore Giombanco, Filippo Marino, Rosario Davide Stracquadaini
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Publication number: 20210064070Abstract: In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.Type: ApplicationFiled: August 27, 2019Publication date: March 4, 2021Inventors: MICHAEL RYAN HANSCHKE, FILIPPO MARINO, SUNGLYONG KIM, TOBIN DANIEL HAGAN, RICHARD LEE VALLEY, BHARATH BALAJI KANNAN, SALVATORE GIOMBANCO, SEETHARAMAN SRIDHAR
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Patent number: 10936000Abstract: In an example, a circuit includes a first power switch device coupled between a voltage input and an output terminal, the first power switch device having a control input. A voltage divider circuit includes a first resistor and a second resistor. The first resistor is coupled between the voltage input and a sense node between the first resistor and the second resistor. The second resistor has a first terminal coupled to the sense node and a second terminal. A second switch device is coupled between the second terminal of the second resistor and an electrical ground terminal. A voltage clamp is coupled between the sense node and the electrical ground terminal.Type: GrantFiled: August 27, 2019Date of Patent: March 2, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Ryan Hanschke, Filippo Marino, Sunglyong Kim, Tobin Daniel Hagan, Richard Lee Valley, Bharath Balaji Kannan, Salvatore Giombanco, Seetharaman Sridhar
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Patent number: 10784785Abstract: A switch-mode power supply includes a power transistor, a transformer, and detection circuitry. The transformer includes a primary winding that is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to a source terminal of the power transistor. The detection circuitry is operable to monitor signal present on the drain terminal via parasitic drain-source capacitance of the power transistor while the power transistor is switched off, and to detect demagnetization of a secondary winding of the transformer via the monitored signal.Type: GrantFiled: December 21, 2017Date of Patent: September 22, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Salvatore Giombanco, Filippo Marino
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Patent number: 10601422Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.Type: GrantFiled: November 10, 2017Date of Patent: March 24, 2020Assignee: Texas Instruments IncorporatedInventors: Yongxi Zhang, Sameer P. Pendharkar, Philip L. Hower, Salvatore Giombanco, Filippo Marino, Seetharaman Sridhar
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Publication number: 20190260289Abstract: In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.Type: ApplicationFiled: December 14, 2018Publication date: August 22, 2019Inventors: Joseph Michael LEISTEN, Salvatore GIOMBANCO, Filippo MARINO, Rosario Davide STRACQUADAINI
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Publication number: 20190199196Abstract: A switch-mode power supply includes a power transistor, a transformer, and detection circuitry. The transformer includes a primary winding that is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to a source terminal of the power transistor. The detection circuitry is operable to monitor signal present on the drain terminal via parasitic drain-source capacitance of the power transistor while the power transistor is switched off, and to detect demagnetization of a secondary winding of the transformer via the monitored signal.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Salvatore GIOMBANCO, Filippo MARINO
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Patent number: 10186964Abstract: At least some aspects of the present disclosure provide for a circuit. In one example, the circuit includes a logic circuit having multiple inputs and multiple outputs, a calculated discontinuous conduction (DCM) (TDCM) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, an on-time (TON) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, and a hysteresis timer having an input coupled to one of the logic circuit outputs and multiple outputs coupled to multiple of the logic circuit inputs.Type: GrantFiled: April 2, 2018Date of Patent: January 22, 2019Assignee: Texas Instruments IncorporatedInventors: Michael Ryan Hanschke, Salvatore Giombanco, John C. Vogt, Filippo Marino, Joseph Michael Leisten, Ananthakrishnan Viswanathan
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Patent number: 10141852Abstract: A circuit for use in an LLC converter to control diode conduction time includes a secondary side controller, the secondary side controller configured to monitor voltage, measure a diode conduction time for the LLC converter, in response to determining that the diode conduction time is greater that a target time, increase the on-time for the first switch, and in response to determining that the diode conduction time is less than a target time, decrease the on-time for the first switch.Type: GrantFiled: December 30, 2016Date of Patent: November 27, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Antonio Amoroso, Filippo Marino, Salvatore Giombanco
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Publication number: 20180191253Abstract: A circuit for use in an LLC converter to control diode conduction time includes a secondary side controller, the secondary side controller configured to monitor voltage, measure a diode conduction time for the LLC converter, in response to determining that the diode conduction time is greater that a target time, increase the on-time for the first switch, and in response to determining that the diode conduction time is less than a target time, decrease the on-time for the first switch.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: Antonio Amoroso, Filippo Marino, Salvatore Giombanco
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Publication number: 20180097517Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.Type: ApplicationFiled: November 10, 2017Publication date: April 5, 2018Inventors: Yongxi Zhang, Sameer P. Pendharkar, Philip L. Hower, Salvatore Giombanco, Filippo Marino, Seetharaman Sridhar
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Patent number: 9843322Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.Type: GrantFiled: March 11, 2016Date of Patent: December 12, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yongxi Zhang, Sameer P. Pendharkar, Philip L. Hower, Salvatore Giombanco, Filippo Marino, Seetharaman Sridhar
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Publication number: 20170264289Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.Type: ApplicationFiled: March 11, 2016Publication date: September 14, 2017Inventors: Yongxi Zhang, Sameer P. Pendharkar, Philip L. Hower, Salvatore Giombanco, Filippo Marino, Seetharaman Sridhar
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Patent number: 9734456Abstract: Determination of a user-specific likelihood of incident occurrence at a geographic location may be performed. User information, historical incident information, contextual information, and/or other information may be obtained. User information may include user demographic information, user behavior information, user social information, and/or other user related information. Historical incident information may include data relating to crime, mortality, injury, morbidity rates and may be obtained from local law enforcement, local Departments of Motor Vehicles, national security agency such as the Federal Bureau of Investigation, foreign security agency such as the Central Intelligence Agency, international criminal policy organization such as Interpol, national public health agency such as Center for Disease Control, international public health agency such as World Health Organization and/or other sources.Type: GrantFiled: April 28, 2016Date of Patent: August 15, 2017Inventor: Filippo Marino
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Patent number: 8811037Abstract: Peak current in a switching converter is controlled using a closed loop to compensate for error caused by delay time in the switching transistor and control logic. A reference value is established that represents a target current value. A compensated reference value is derived from the reference value by the closed loop. A periodic inductor current is formed in the switching converter in response to the compensated reference value. An error signal is formed that is indicative of an amount of time the inductor current exceeds the target current value. The compensated reference value is dynamically adjusted by the compensation closed loop to minimize the error signal.Type: GrantFiled: September 5, 2011Date of Patent: August 19, 2014Assignee: Texas Instruments IncorporatedInventor: Filippo Marino
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Patent number: 8576930Abstract: A receiver of a signal communication apparatus; the apparatus including a transmitter adapted to transmit coded signals, the receiver for receiving the signal and a wireless interface interposed between the transmitter and the receiver and having a transmitting antenna and a receiving antenna. The receiver includes a decoder configured to decode the received signal and circuitry coupled to the receiving antenna and capable of triggering the decoder if the value of the received signal is outside a logical hysteresis having a first logic threshold having a value smaller than the value of the direct current component of the received signal and a second logic threshold having a value greater than the value of the direct current component of the received signal.Type: GrantFiled: July 29, 2010Date of Patent: November 5, 2013Assignee: STMicoelectronics S.r.l.Inventors: Giovanni Lombardo, Salvatore Giombanco, Michele Grande, Salvatore Tumminaro, Filippo Marino