Patents by Inventor Filippos Papadatos
Filippos Papadatos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9735268Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.Type: GrantFiled: August 4, 2016Date of Patent: August 15, 2017Assignee: International Business Machines CorporationInventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
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Patent number: 9559202Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.Type: GrantFiled: October 27, 2014Date of Patent: January 31, 2017Assignee: International Business Machines CorporationInventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
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Publication number: 20160343664Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.Type: ApplicationFiled: August 4, 2016Publication date: November 24, 2016Inventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
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Patent number: 9425309Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.Type: GrantFiled: September 11, 2014Date of Patent: August 23, 2016Assignee: International Business Machines CorporationInventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
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Patent number: 9252050Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.Type: GrantFiled: September 11, 2012Date of Patent: February 2, 2016Assignees: International Business Machines Corporation, STMicroelectronics, Inc.Inventors: Lindsey H. Hall, Michael Hatzistergos, Ahmet S. Ozcan, Filippos Papadatos, Yiyi Wang
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Patent number: 9230857Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.Type: GrantFiled: October 23, 2014Date of Patent: January 5, 2016Assignees: International Business Machines Corporation, St. Microelectronics Inc.Inventors: Lindsey H. Hall, Michael Hatzistergos, Ahmet S. Ozcan, Filippos Papadatos, Yiyi Wang
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Publication number: 20150111374Abstract: Embodiments of present invention provide a method of forming semiconductor devices. The method includes creating an opening in a semiconductor structure; depositing a first layer of metal inside the opening with the first layer of metal partially filling up the opening; modifying a top surface of the first layer of metal in an etching process; passivating the modified top surface of the first layer of metal to form a passivation layer; and depositing a second layer of metal directly on top of the passivation layer.Type: ApplicationFiled: October 18, 2013Publication date: April 23, 2015Applicant: International Business Machines CorporationInventors: Ruqiang Bao, Domingo A. Ferrer, Filippos Papadatos, Daniel P. Stambaugh
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Patent number: 9006801Abstract: A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.Type: GrantFiled: January 25, 2011Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
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Publication number: 20150044845Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.Type: ApplicationFiled: October 27, 2014Publication date: February 12, 2015Inventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
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Publication number: 20140374844Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.Type: ApplicationFiled: September 11, 2014Publication date: December 25, 2014Inventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
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Publication number: 20140073131Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.Type: ApplicationFiled: September 11, 2012Publication date: March 13, 2014Applicants: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lindsey H. Hall, Michael Hatzistergos, Ahmet S. Ozcan, Filippos Papadatos, Yiyi Wang
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Patent number: 8614107Abstract: An electrical structure comprises a dielectric layer present on a semiconductor substrate. A contact opening is present through the dielectric layer. A nickel-tungsten alloy silicide is formed over the semiconductor substrate within the contact opening. A tungsten-containing nucleation layer formed within the contact opening covers the nickel-tungsten alloy silicide and at least a portion of a sidewall of the contact opening. A tungsten contact is formed within the contact opening and separated from the nickel-tungsten alloy silicide and at least a portion of the sidewall by the tungsten-containing nucleation layer.Type: GrantFiled: February 18, 2013Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Christian Lavoie, Ahmet S. Ozcan, Filippos Papadatos
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Patent number: 8614106Abstract: A liner-less tungsten contact is formed on a nickel-tungsten silicide with a tungsten rich surface. A tungsten-containing layer is formed using tungsten-containing fluorine-free precursors. The tungsten-containing layer may act as a glue layer for a subsequent nucleation layer or as the nucleation layer. The tungsten plug is formed by standard processes. The result is a liner-less tungsten contact with low resistivity.Type: GrantFiled: November 18, 2011Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Christian Lavoie, Ahmet S. Ozcan, Filippos Papadatos
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Patent number: 8552502Abstract: An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.Type: GrantFiled: March 23, 2012Date of Patent: October 8, 2013Assignee: International Business Machines CorporationInventors: Zhengwen Li, Michael P. Chudzik, Unoh Kwon, Filippos Papadatos, Andrew H. Simon, Keith Kwong Hon Wong
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Publication number: 20130127058Abstract: A liner-less tungsten contact is formed on a nickel-tungsten silicide with a tungsten rich surface. A tungsten-containing layer is formed using tungsten-containing fluorine-free precursors. The tungsten-containing layer may act as a glue layer for a subsequent nucleation layer or as the nucleation layer. The tungsten plug is formed by standard processes. The result is a liner-less tungsten contact with low resistivity.Type: ApplicationFiled: November 18, 2011Publication date: May 23, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Lavoie, Ahmet S. Ozcan, Filippos Papadatos
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Patent number: 8232148Abstract: An electrical device is provided with a p-type semiconductor device having a first gate structure that includes a gate dielectric on top of a semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.Type: GrantFiled: March 4, 2010Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Zhengwen Li, Michael P. Chudzik, Unoh Kwon, Filippos Papadatos, Andrew H. Simon, Keith Kwong Hon Wong
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Publication number: 20120187460Abstract: A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.Type: ApplicationFiled: January 25, 2011Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
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Publication number: 20120187420Abstract: An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.Type: ApplicationFiled: March 23, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhengwen Li, Michael P. Chudzik, Unoh Kwon, Filippos Papadatos, Andrew H. Simon, Keith Kwong Hon Wong
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Publication number: 20110215409Abstract: An electrical device is provided with a p-type semiconductor device having a first gate structure that includes a gate dielectric on top of a semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.Type: ApplicationFiled: March 4, 2010Publication date: September 8, 2011Applicant: International Business Machines CorporationInventors: Zhengwen Li, Michael P. Chudzik, Unoh Kwon, Filippos Papadatos, Andrew H. Simon, Keith Kwong Hon Wong
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Patent number: 7993987Abstract: A method includes providing a substrate including a non-insulative, silicon-including region for silicidation, the substrate including one or more contaminants at a top surface thereof. A getter layer is deposited over the non-insulative, silicon-including region, the getter layer reacting with at least one of the one or more contaminants in the non-insulative, silicon-including region at approximately room temperature. The getter layer is removed, and siliciding of the non-insulative, silicon-including region is performed.Type: GrantFiled: October 14, 2010Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Randolph F. Knarr, Christian Lavoie, Ahmet S. Ozcan, Filippos Papadatos