Abstract: A switching device comprising at least one ingress port and at least one egress port. The switching device is arranged to receive data packets through said at least one ingress port and to forward received data packets to respective ones of said at least one egress port. The switching device further comprises a primary buffer arranged to store data packets received via at least one of said at least one ingress ports and a secondary buffer associated with the primary buffer. The switching device is adapted to select a data packet from said primary buffer and if but only if said secondary buffer satisfies a least one first predetermined criterion, transfer said selected data packet to said secondary buffer.

Abstract: A switching device comprising a plurality of ingress ports and a plurality of egress ports. The switching device is arranged to receive data packets through said ingress ports and to forward received data packets to respective ones of said egress ports. The switching device further comprises an ingress module for each of said ingress ports, each ingress module being arranged to receive data packets from a respective single one of said ingress ports and to store the received data packets in one of a plurality of data structures provided by the ingress module, each ingress module being further configured to select a data packet from one of said plurality of data structures, and to request permission to transmit the selected data packet to an egress port.

Abstract: A method of processing data packets, each data packet being associated with one of a plurality of entities. The method comprises storing a data packet associated with a respective one of said plurality of entities in a buffer, storing state parameter data associated with said stored data packet, the state parameter data being based upon a value of a state parameter associated with said respective one of said plurality of entities, and processing a data packet in said buffer based upon said associated state parameter data.

Abstract: A method of switching data packets between an input and a plurality of outputs of a switching device. The switching device comprises a memory arranged to store a plurality of data structures, each data structure being associated with one of said outputs. The method comprises receiving a first data packet at said input, and storing said first data packet in a data structure associated with an output from which said data packet is to be transmitted. If said first data packet is intended to be transmitted from a plurality of said outputs, indication data is stored in each data structure associated with an output from which said first data packet is to be transmitted, but said first data packet is stored in only one of said data structures. The first data packet is transmitted from said data structure to the or each output from which the first data packet is to be transmitted.

Abstract: A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side.

Abstract: A switch for connection in a network of other like switches and includes memory for storing data packets, a control system arranged to control the switch to, upon receipt at one of the ingress or egress ports of notification of congestion at a downstream congested port, either store at said ingress port or egress port data packets received for said congested port or to communicate with an upstream port for storage at said upstream port of data packets destined for the congested port, and in dependence on the current of stored data, to send a message to a further upstream port informing the further upstream port of the congestion downstream. The memory is provided substantially only at the ingress ports or the egress ports of the switch.

Abstract: A method of queuing data packets, said data packets comprising data packets of a first packet type and data packets of a second packet type. The method comprises grouping received packets of said first and second packet types into an ordered series of groups, each group comprising at least one packet, maintaining a group counter indicating the number of groups at the beginning of the series of groups comprising only packets of the second packet type, and transmitting a packet. A packet of the second packet type is available for transmission if but only if the group counter is indicative that the number of groups at the beginning of the series of groups comprising only packets of the second packet type is greater than zero.

Abstract: A method of congestion management within a switch or network of connected switches is provided, wherein the or each of the switches has a plurality of ingress ports and a plurality of egress ports. The method involves, when congestion is detected at a first ingress or egress port, sending a message to an upstream port connected to the first ingress or egress port indicating that congestion has occurred at a particular port and requesting storage at the upstream port of data packets destined for that port; and, in dependence on the amount of data packets destined for the congested port stored at the upstream port, sending from the upstream port to a further upstream port a message informing the further upstream port of the congestion at the congested port, the further upstream port storing at the further upstream port data packets destined for the congested port.

Abstract: A first transparent latch receives a first synchronised signal changing its logic state synchronously with respect to a clock signal. A second transparent latch receives a second synchronised signal output by the first latch. When the clock signal has a first logic state the first latch has a non-responsive state and the second latch has a responsive state, and when the clock signal has a second logic state the first latch has the responsive state and the second latch has the non-responsive state. The change in logic state of a third synchronised signal output by the second latch is guaranteed to occur in a particular half-cycle of the clock signal, irrespective of process/voltage/temperature (PVT) variations of the circuitry.

Abstract: In a semiconductor integrated circuit device (700) in which variation in a minimum propagation time of a transmission signal from a source node (SN) to a destination node (DN) is sufficiently large, relative to a clock period (T) at an intended clock frequency of the device, to cause variation in a clock cycle in which the transmission signal reaches the destination node (DN) a plurality of clocked elements (8000 to 8003) are connected in series between the source and destination nodes for causing a shift signal (SS0 to SS4), representing the transmission signal present at the source node (SN) in a first clock cycle, to be shifted from the source node (SN) to the destination node (DN) through the series of clocked elements (8000 to 8003) one clocked element (800i) per predetermined number of clock cycles.

Abstract: Scheduling circuitry, for use for example in an ATM network unit to schedule cell transmissions, includes a master calendar (1) for holding entries corresponding respectively to events (cell transmissions) that are to occur within a preselected master-calendar scheduling range (SR), and a slave calendar (12) for holding entries corresponding respectively to events that are to occur beyond that scheduling range. When an event is to be scheduled, calendar control circuitry (24) makes an entry corresponding thereto in the slave calendar (12) if the interval between a current time and a desired scheduling time for the event exceeds said scheduling range. The entry in the slave calendar includes timing information representing the desired scheduling time. The calendar control circuitry monitors the entries in the slave calendar (12) and causes an entry therein whose corresponding event becomes within the scheduling range to be transferred to the master calendar (1).

Abstract: In a memory access method used with a synchronous dynamic random access memory (SDRAM) having first and second banks, each information item is allocated respective first and second storage locations in the memory. The first and second storage locations are in the first and second banks (Bank 0, Bank 1) respectively. When, in the same time slot, it is required to write a first such information item (W) in the memory and to read a second such information item (R) from the memory, it is firstly determined which of the first and second banks currently holds the second information item (R). The first information item (W) is written in the first storage location allocated thereto if the determined bank is the second bank and is written in the second storage location allocated thereto if the determined bank is the first bank. The second information item (R) is read from the determined bank after the first information is written.

Abstract: In a semiconductor integrated circuit device (700) in which variation in a minimum propagation time of a transmission signal from a source node (SN) to a destination node (DN) is sufficiently large, relative to a clock period (T) at an intended clock frequency of the device, to cause variation in a clock cycle in which the transmission signal reaches the destination node (DN) a plurality of clocked elements (8000 to 8003) are connected in series between the source and destination nodes for causing a shift signal (SS0 to SS4), representing the transmission signal present at the source node (SN) in a first clock cycle, to be shifted from the source node (SN) to the destination node (DN) through the series of clocked elements (8000 to 8003) one clocked element (800i) per predetermined number of clock cycles.

Abstract: In a memory access method used with a synchronous dynamic random access memory (SDRAM) having first and second banks, each information item is allocated respective first and second storage locations in the memory. The first and second storage locations are in the first and second banks (Bank 0, Bank 1) respectively.

Abstract: In a memory access method used with a synchronous dynamic random access memory (SDRAM) having first and second banks, each information item is allocated respective first and second storage locations in the memory. The first and second storage locations are in the first and second banks (Bank 0, Bank 1) respectively. When, in the same time slot, it is required to write a first such information item (W) in the memory and to read a second such information item (R) from the memory, it is firstly determined which of the first and second banks currently holds the second information item (R). The first information item (W) is written in the first storage location allocated thereto if the determined bank is the second bank and is written in the second storage location allocated thereto if the determined bank is the first bank. The second information item (R) is read from the determined bank after the first information is written.

Abstract: A first transparent latch (22) receives a first synchronised signal (S1) which changes its logic state synchronously with respect to a clock signal (CLK). A second transparent latch (24) receives a second synchronised signal (S2) output by the first latch (22). When the clock signal has a first logic state (H) the first latch (22) has a non-responsive state and the second latch has a responsive state, and when the clock signal has a second logic state (L) the first latch has the responsive state and the second latch has the non-responsive state.

Abstract: A data receiving device, for receiving data from an ATM network, has a data storage circuit (38) for allocating preselected virtual channels of the network with respect to corresponding storage regions (5r) in a local memory (5) connected with the device. The storage regions are in the form of linked lists. When data items belonging to the different preselected virtual channels are received in succession by the device, the data storage circuit (38) stores those items in the storage regions that correspond respectively to the items' virtual channels. As a result, transfer of the received data items from the local memory (5) to a further connected apparatus (7) connected with the device, is performed in a different channel order form that in which those items were received by the device from the network. The latter transfer may be performed by the connected further apparatus or by a data transfer circuit (40) of the device.

Abstract: A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes: USER, HOLD, SHIFT and SELF-TEST modes. These modes are controlled by shifting a control function into a control shift register. When the shifting of the control shift register stops, a command is automatically loaded from the control shift register (or another source) into a command register, which controls the serial shift paths. The provision of a separate command register allows a new control function to be shifted into the control shift register while a preceding command is still active in the command register.

Abstract: A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes; USER, HOLD, SHIFT and SELF-TEST modes. Shifting of a path is achieved by putting the path into HOLD mode and then, at each of a series of transfer pulses (TR), putting the path into shift mode for one clock beat. This allows the shifting to be performed at a lower rate than the internal clock rate of the chip; in particular, it can be performed at a rate compatible with a relatively slow diagnostic processor.

Abstract: A digital integrated circuit comprises a number of registers each of which comprises several data bits and at least one control bit cell. In a normal operation state, all the registers act as parallel input/output registers. In a SHIFT state, the data bits and control bit cells of all the registers are linked together to from a serial shift path between a pair of external terminals allowing test data to be shifted in or out as required. In a TEST state, each register is set into one of a number of test modes, controlled by the test bit cells of that register. The test modes include a test generate mode in which the register acts as a pseudo-random number generator, and a test analyze mode in which it acts as a digital signature analyzer.