Abstract: A duty cycle correction circuit has a delay line comprising a plurality of current-starved inverters coupled together in series. An input of a first current-starved inverter receives an input clock signal. A relatively weak inverter is coupled in parallel with each of the current-starved inverters. A low pass filter having an operational amplifier has a differential input coupled to the output of the delay line for receiving an output clock signal. A single-ended output of the operational amplifier is coupled to current source and current sink transistors of each of the current-starved inverters to control the amount of delay provided by the delay line. The low pass filter corrects the duty cycle of the input clock signal so that the output clock signal has a 50 percent duty cycle. The relatively weak parallel-connected inverters insure that no clock pulses are skipped if the current-starved inverters fail to transition.

Abstract: A data density independent clock and data recovery system includes a lock phase adjust charge pump operably coupled to receive phase information and transition information from a phase detector and to produce a current signal, responsive to the phase information and transition information, to a loop filter that converts the current signal to a control voltage signal operably coupled to a voltage controlled oscillator that produces a clock signal to the phase detector based on the control voltage signal. The lock phase adjust charge pump includes a phase charge pump, a transition charge pump, a programmable DC bias current sink, and two programmable offset bias current sinks. The transition charge pump includes a programmable transition current sink. The control logic operates under external control to adjust the currents conducted by the transition charge pump, the programmable DC bias current sink, and the two programmable offset bias current sinks.