Abstract: A non-planar body (1) comprising a dome body (2) having an apex (3) and an outer periphery, the apex (3) located on a first plane (4) and the outer periphery located on a second plane (6) substantially parallel to the first plane (4). A peripheral body (5) extends at least partially around the outer periphery of the dome body (2), and at an angle (7) of less than 180° with respect to a tangent (8) relative to the dome body (2) at the outer periphery of the dome body (2), the angle (7) being measured at an outer surface of the dome body (2). Any of the dome body (2) and the peripheral body are formed from polycrystalline diamond.

Abstract: A method of fabricating a semiconductor device structure includes: providing a substrate comprising a layer of compound semiconductor material; forming a seed layer of nano-crystalline diamond having a layer thickness in a range 5 to 50 nm on the layer of compound semiconductor material; and growing a layer of polycrystalline CVD diamond on the seed layer using a chemical vapour deposition (CVD) technique. An effective thermal boundary resistance (TBReff) at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m2K/GW.

Abstract: Methods of fabricating compound semiconductor device structures having polycrystalline CVD diamond. The method includes: providing a substrate that has a layer of single crystal compound semiconductor material; forming a bonding layer on a surface of the substrate, the bonding layer having a thickness of less than 25 nm and a thickness variation of no more than 15 nm; and growing a layer of polycrystalline diamond on the bonding layer using a chemical vapor deposition technique. The effective thermal boundary resistance at the interface between the layer of single crystal compound semiconductor material and the layer of polycrystalline CVD diamond material is less than 25 m2K/GW. The layer of single crystal compound semiconductor material has one or both of the following characteristics: a charge mobility of at least 1200 cm2V?1s?1; and a sheet resistance of no more than 700 ?/square.

Abstract: A method of fabricating a semiconductor device structure includes: providing a substrate comprising a layer of compound semiconductor material; forming a seed layer of nano-crystalline diamond having a layer thickness in a range 5 to 50 nm on the layer of compound semiconductor material; and growing a layer of polycrystalline CVD diamond on the seed layer using a chemical vapour deposition (CVD) technique. An effective thermal boundary resistance (TBReff) at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m2K/GW.

Abstract: A semiconductor device structure comprising: a layer of single crystal compound semiconductor material; and a layer of polycrystalline CVD diamond material, wherein the layer of polycrystalline CVD diamond material is bonded to the layer of single crystal compound semiconductor material via a bonding layer having a thickness of less than 25 nm and a thickness variation of no more than 15 nm, wherein an effective thermal boundary resistance (TBReff) as measured by transient thermoreflectance at an interface between the layer of single crystal compound semiconductor material and the layer of polycrystalline CVD diamond material is less than 25 m2 K/GW with a variation of no more than 12 m2 K/GW as measured across the semiconductor device structure, and wherein the layer of single crystal compound semiconductor material has one or both of the following characteristics: a charge mobility of at least 1200 cm2 V?1 s?1; and a sheet resistance of no more than 700 ?/square.

Abstract: A semiconductor device structure comprising: a layer of compound semiconductor material; and a layer of polycrystalline CVD diamond material, wherein the layer of polycrystalline CVD diamond material is bonded to the layer of compound semiconductor material via a layer of nano-crystalline diamond which is directly bonded to the layer of compound semiconductor material, the layer of nano-crystalline diamond having a thickness in a range 5 to 50 nm and configured such that an effective thermal boundary resistance (TBReff) as measured by transient thermoreflectance at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m2K/GW.

Abstract: A semiconductor device structure includes a layer of single crystal compound semiconductor material; and a layer of polycrystalline CVD diamond material. The layer of polycrystalline CVD diamond material is bonded to the layer of single crystal compound semiconductor material via a bonding layer having a thickness of less than 25 nm and a thickness variation of no more than 15 nm. The effective thermal boundary resistance as measured by transient thermoreflectance at an interface between the layer of single crystal compound semiconductor material and the layer of polycrystalline CVD diamond material is less than 25 m2K/GW with a variation of no more than 12 m2K/GW as measured across the semiconductor device structure. The layer of single crystal compound semiconductor material has one or both of the following characteristics: a charge mobility of at least 1200 cm2V?1s?1; and a sheet resistance of no more than 700 ?/square.

Abstract: A semiconductor device structure includes a layer of single crystal compound semiconductor material; and a layer of polycrystalline CVD diamond material. The layer of polycrystalline CVD diamond material is bonded to the layer of single crystal compound semiconductor material via a bonding layer having a thickness of less than 25 nm and a thickness variation of no more than 15 nm. The effective thermal boundary resistance as measured by transient thermoreflectance at an interface between the layer of single crystal compound semiconductor material and the layer of polycrystalline CVD diamond material is less than 25 m2K/GW with a variation of no more than 12 m2K/GW as measured across the semiconductor device structure. The layer of single crystal compound semiconductor material has one or both of the following characteristics: a charge mobility of at least 1200 cm2V?1s?1; and a sheet resistance of no more than 700 ?/square.

Abstract: A semiconductor device structure comprising: a layer of compound semiconductor material; and a layer of polycrystalline CVD diamond material, wherein the layer of polycrystalline CVD diamond material is bonded to the layer of compound semiconductor material via a layer of nano-crystalline diamond which is directly bonded to the layer of compound semiconductor material, the layer of nano-crystalline diamond having a thickness in a range 5 to 50 nm and configured such that an effective thermal boundary resistance (TBReff) as measured by transient thermoreflectance at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m2K/GW.

Abstract: Disclosed is a semiconductor device structure including a III-V compound semiconductor material layer, a polycrystalline CVD diamond material layer, and an interface region, having a diamond nucleation layer, between the III-V compound semiconductor material layer and the polycrystalline CVD diamond material layer. A Raman signal generated from a region having the diamond nucleation layer exhibits an sp3 carbon peak at 1332 cm?1 having a full width half-maximum of no more than 5.0 cm?1. The Raman signal further exhibits one or both of the following characteristics: (i) an sp2 carbon peak at 1550 cm?1 having a height no more than 20% of a height of the sp3 carbon peak; and (ii) the sp3 carbon peak at 1332 cm?1 is no less than 10% of local background intensity. The diamond nucleation layer further includes an average nucleation density range of 1×108 cm?2 to 1×1012 cm?2.

Abstract: Disclosed is a semiconductor device structure including a III-V compound semiconductor material layer, a polycrystalline CVD diamond material layer, and an interface region, having a diamond nucleation layer, between the III-V compound semiconductor material layer and the polycrystalline CVD diamond material layer. A Raman signal generated from a region having the diamond nucleation layer exhibits an sp3 carbon peak at 1332 cm?1 having a full width half-maximum of no more than 5.0 cm?1. The Raman signal further exhibits one or both of the following characteristics: (i) an sp2 carbon peak at 1550 cm?1 having a height no more than 20% of a height of the sp3 carbon peak; and (ii) the sp3 carbon peak at 1332 cm?1 is no less than 10% of local background intensity. The diamond nucleation layer further includes an average nucleation density range of 1×108 cm?2 to 1×1012 cm?2.

Abstract: A semiconductor device structure includes a layer of III-V compound semiconductor material, a layer of polycrystalline CVD diamond material, and an interface region with a diamond nucleation layer. A Raman signal of the diamond nucleation layer exhibits an sp3 carbon peak at 1332 cm?1 having a full width half maximum of no more than 5.0 cm?1, and one or both of: (i) an sp2 carbon peak at 1550 cm?1 having a height which is no more than 20% of a height of the sp3 carbon peak at 1332 cm?1 after background subtraction when using a Raman excitation source at 633 nm; and (ii) the sp3 carbon peak at 1332 cm?1 is no less than 10% of local background intensity in a Raman spectrum using a Raman excitation source at 785 nm. An average nucleation density at a nucleation surface is no less than 1×108 cm?2 and no more than 1×1012 cm?2.

Abstract: A semiconductor device structure comprising: a layer of III-V compound semiconductor material; a layer of polycrystalline CVD diamond material; and an interface region between the layer of III-V compound semiconductor material and the layer of polycrystalline CVD diamond material, the interface region including a diamond nucleation layer of polycrystalline CVD diamond which is formed during an initial nucleation phase of polycrystalline CVD diamond growth over a substrate comprising the layer of III-V compound semiconductor material, wherein the diamond nucleation layer is such that a Raman signal generated by a laser focused on a region comprising the diamond nucleation layer exhibits an sp3 carbon peak at 1332 cm?1 having a full width half-maximum of no more than 5.

Abstract: Methods for manufacturing semiconductor wafer structures are described which exhibit improved lifetime and reliability. The methods comprise transferring an active semiconductor layer structure from a native non-lattice-matched semiconductor growth substrate to a working substrate, wherein strain-matching layers, and optionally a portion of the active semiconductor layer structure, are removed. In certain embodiment, the process of attaching the active semiconductor layer structure to the working substrate includes annealing at an elevated temperature for a specified time.

Abstract: Methods for integrating wide-gap semiconductors, and specifically, gallium nitride epilayers with synthetic diamond substrates are disclosed. Diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited or formed on a layered structure that comprises at least one layer made out of gallium nitride. Methods for manufacturing GaN-on-diamond wafers with low bow and high crystalline quality are disclosed along with preferred choices for manufacturing GaN-on-diamond wafers and chips tailored to specific applications.

Abstract: Methods for integrating wide-gap semiconductors, and specifically, gallium nitride epilayers with synthetic diamond substrates are disclosed. Diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited or formed on a layered structure that comprises at least one layer made out of gallium nitride. Methods for manufacturing GaN-on-diamond wafers with low bow and high crystalline quality are disclosed along with preferred choices for manufacturing GaN-on-diamond wafers and chips tailored to specific applications.

Abstract: The invention is a method for growing a critical adherent diamond layer on a substrate by Chemical Vapor Deposition (CVD) and the article produced by the method. The substrate can be a compound semiconductor coated with an adhesion layer. The adhesion layer is preferably a dielectric, such as silicon nitride, silicon carbide, aluminum nitride or amorphous silicon, to name some primary examples. The typical thickness of the adhesion layer is one micrometer or less. The resulting stack of layers, (e.g. substrate layer, adhesion layer and diamond layer) is structurally free of plastic deformation and the diamond layer is well adherent to the dielectric adhesion layer such that it can be processed further, such as by increasing the thickness of the diamond layer to a desired level, or by subjecting it to additional thin film fabrication process steps. In addition to preventing plastic deformation of the layer stack, the process also reduces the formation of soot during the CVD process.

Abstract: A method for polishing the surface of a diamond film with a low power density plasma in a reactor which comprises disposing O.sub.2 gas and a fluorinated gas such as SF.sub.6, NF.sub.3, and C.sub.2 F.sub.6 in the reactor, providing power to the reactor so that the power density in the reactor is between about 1.0 watts/cm.sup.2 and about 1.1 watts/cm.sup.2 for a first duration, and maintaining temperature in the reactor at between about 200.degree. to about 400.degree.. The method may alternatively comprise disposing a sputter gas such as Ar,O.sub.2 or N.sub.2 in the reactor, providing power to the reactor so that the power density in the reactor is between about 3.0 watts/cm.sup.2 and about 7.5 watts/cm.sup.2 for a first duration, and performing a sputter etch, disposing O.sub.2 gas and a fluorinated gas such as SF.sub.6, NF.sub.3, and C.sub.2 F.sub.6 in the reactor, and providing power to the reactor so that the power density in the reactor is between about 1.5 watts/cm.sup.2 and about 3.0 watts/cm.sup.