Abstract: A method for validating timing violations in a testbench is provided. The method includes obtaining the timing requirements for a design under test from a first file. The timing requirements for the design may be entered as an input to a verification tool. Then, based on the timing requirements of the user, a place and route operation is performed resulting in a design layout. Following the place and route operation, timing results are obtained for the design layout. The timing results may be obtained through simulation. From the timing results, timing values are extracted at the input level so that the inputs may be driven based on those timing values. The timing values compensate for any timing violations that may have resulted from the timing models of the verification tool.