Patents by Inventor Florence Pon
Florence Pon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948917Abstract: Embodiments described herein provide a semiconductor package comprising multiple dies encapsulated in multiple molding compounds. In one example, a semiconductor package comprises: a first die or die stack on a substrate; a first molding compound encapsulating the first die or die stack on the substrate; a second die or die stack on the first molding compound; and a second molding compound encapsulating the second die or die stack and at least one portion of the first molding compound. In this example, the first die or die stack is electrically coupled to the substrate using a first wire bond and the second die or die stack is electrically coupled to the substrate using a second wire bond. Additionally, the first molding compound encapsulates the first wire bond and the second molding compound encapsulates the second wire bond. Furthermore, a footprint of the second die overlaps a footprint of the first die.Type: GrantFiled: April 23, 2019Date of Patent: April 2, 2024Assignee: Intel CorporationInventors: Florence Pon, Yi Xu, James Zhang, Yuhong Cai, Tyler Leuten, William Glennan, Hyoung Il Kim
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Patent number: 11901264Abstract: Embodiments disclosed herein include electronic packages with chocked flow cooling. In an embodiment, an electronic package may comprise a package substrate, a die electrically and mechanically coupled to the package substrate, and a lid over the die. In an embodiment, the lid has a first opening and a second opening that is opposite from the first opening. In an embodiment, the electronic package may further comprise a coolant plate covering the first opening. In an embodiment, the coolant plate comprises a first surface facing away from the die and a second surface facing the die, and a plurality of vents from the first surface to the second surface. In an embodiment, the first openings of the plurality of vents have a first dimension and second openings of the plurality of vents have a second dimension that is smaller than the first dimension.Type: GrantFiled: October 31, 2018Date of Patent: February 13, 2024Assignee: SK hynix NAND Product Solutions Corp.Inventors: Mark Forsnes, Yuhong Cai, Florence Pon, Yi Xu
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Publication number: 20230359336Abstract: Apparatuses, methods and storage medium associated with computer-assisted or autonomous driving (CA/AD) vehicles are disclosed herein. In embodiments, CA/AD vehicles are members of a CA/AD vehicle social network (CASN) in which various CA/AD vehicles may form connections or relationships with one another. CA/AD vehicles that have an existing relationship or connection may share CASN information with one another. The CASN information may include authenticated and/or proprietary information. Other embodiments are also described and claimed.Type: ApplicationFiled: July 13, 2023Publication date: November 9, 2023Inventors: Fatema Adenwala, Ankitha Chandran, Nageen Himayat, Florence Pon, Divya Vijayaraghavan
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Patent number: 11704007Abstract: Apparatuses, methods and storage medium associated with computer-assisted or autonomous driving (CA/AD) vehicles are disclosed herein. In embodiments, CA/AD vehicles are members of a CA/AD vehicle social network (CASN) in which various CA/AD vehicles may form connections or relationships with one another. CA/AD vehicles that have an existing relationship or connection may share CASN information with one another. The CASN information may include authenticated and/or proprietary information. Other embodiments are also described and claimed.Type: GrantFiled: May 10, 2021Date of Patent: July 18, 2023Assignee: Intel CorporationInventors: Fatema Adenwala, Ankitha Chandran, Nageen Himayat, Florence Pon, Divya Vijayaraghavan
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Patent number: 11658079Abstract: Embodiments described herein are directed to a temporary interconnect for use in testing one or more devices (e.g., one or more dies, inductors, capacitors, etc.) formed in semiconductor package. In one scenario, a temporary interconnect acts an electrical bridge that electrically couples a contact pad on a surface of a substrate and the test pad. Coupling the contact pad and the test pad to each other enables the device(s) coupled the contact pad to be tested. Following testing, the temporary interconnect can be removed or severed so that an electrical break is formed in the conductive path between test pad and the contact pad.Type: GrantFiled: January 17, 2019Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Hyoung Il Kim, Yi Xu, Florence Pon
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Patent number: 11652031Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate an elastomer coupled to the substrate and a plurality of bondfingers on the elastomer. The substrate, the elastomer and the bondfingers are configured to cooperatively expand and retract.Type: GrantFiled: December 13, 2018Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Florence Pon, Yi Xu, Min-Tih Lai
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Patent number: 11599750Abstract: Edge devices utilizing personalized machine learning and methods of operating the same are disclosed. An example edge device includes a model accessor to access a first machine learning model from a cloud service provider. A local data interface is to collect local user data. A model trainer is to train the first machine learning model to create a second machine learning model using the local user data. A local permissions data store is to store permissions indicating constraints on the local user data with respect to sharing outside of the edge device. A permissions enforcer is to apply permissions to the local user data to create a sub-set of the local user data to be shared outside of the edge device. A transmitter is to provide the sub-set of the local user data to a public data repository.Type: GrantFiled: September 28, 2018Date of Patent: March 7, 2023Assignee: Intel CorporationInventors: Maruti Gupta Hyde, Florence Pon, Naissa Conde, Xue Yang, Wei Yee Koay
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Patent number: 11545464Abstract: Embodiments described herein provide techniques for testing a semiconductor package by using a diode to couple a test pad to a contact pad. In one scenario, a package comprises a die stack comprising one or more dies and a molding compound encapsulating the die stack. In this package, a substrate is over the molding compound. Also, a test pad and a contact pad are on a surface of the substrate. The contact pad is coupled to the die stack. A diode couples the test pad to the contact pad. In one example, the test pad is coupled to a P side of the diode's P-N junction and the contact pad is coupled to an N side of the diode's P-N junction. In operation, current can flow from the test pad through the contact pad (and the die stack), but current cannot flow from the contact pad through the test pad.Type: GrantFiled: December 28, 2018Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Yi Xu, Hyoung Il Kim, Florence Pon
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Patent number: 11495547Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of buildup layers, and where each buildup layer has fiber reinforcement. In an embodiment, the electronic package further comprises a reinforcement layer, where the reinforcement layer comprises a buildup layer and fiber reinforcement, and where an orientation of the fibers in the reinforcement layer is different than an orientation of the fibers in the package substrate.Type: GrantFiled: October 15, 2018Date of Patent: November 8, 2022Assignee: Intel CorporationInventors: Florence Pon, Tyler Leuten, Maria Angela Damille Ramiso
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Patent number: 11399434Abstract: Embodiments disclosed herein include modular electronics packages and methods of forming such packages. In an embodiment, the electronics package comprises a first connector module having a notch on a first end and a plurality of surface mount technology (SMT) pads on a second end. In an embodiment, the electronics package further comprises a second connector module having a keyed connector on a first end and a plurality of SMT pads on a second end. In an embodiment, the electronics package further comprises a system in package (SIP) module between the first connector module and the second connector module, the component module electrically and mechanically coupled to the SMT pads of the first connector and the SMT pads of the second connector.Type: GrantFiled: October 11, 2018Date of Patent: July 26, 2022Inventors: Florence Pon, Tyler Leuten, Maria Angela Damille Ramiso
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Publication number: 20210303137Abstract: Apparatuses, methods and storage medium associated with computer-assisted or autonomous driving (CA/AD) vehicles are disclosed herein. In embodiments, CA/AD vehicles are members of a CA/AD vehicle social network (CASN) in which various CA/AD vehicles may form connections or relationships with one another. CA/AD vehicles that have an existing relationship or connection may share CASN information with one another. The CASN information may include authenticated and/or proprietary information. Other embodiments are also described and claimed.Type: ApplicationFiled: May 10, 2021Publication date: September 30, 2021Inventors: Fatema Adenwala, Ankitha Chandran, Nageen Himayat, Florence Pon, Divya Vijayaraghavan
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Patent number: 11036370Abstract: Apparatuses, methods and storage medium associated with computer-assisted or autonomous driving (CA/AD) vehicles are disclosed herein. In embodiments, CA/AD vehicles are members of a CA/AD vehicle social network (CASN) in which various CA/AD vehicles may form connections or relationships with one another. CA/AD vehicles that have an existing relationship or connection may share CASN information with one another. The CASN information may include authenticated and/or proprietary information. Other embodiments are also described and claimed.Type: GrantFiled: September 25, 2018Date of Patent: June 15, 2021Assignee: Intel CorporationInventors: Fatema Adenwala, Ankitha Chandran, Nageen Himayat, Florence Pon, Divya Vijayaraghavan
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Publication number: 20200343221Abstract: Embodiments described herein provide a semiconductor package comprising multiple dies encapsulated in multiple molding compounds. In one example, a semiconductor package comprises: a first die or die stack on a substrate; a first molding compound encapsulating the first die or die stack on the substrate; a second die or die stack on the first molding compound; and a second molding compound encapsulating the second die or die stack and at least one portion of the first molding compound. In this example, the first die or die stack is electrically coupled to the substrate using a first wire bond and the second die or die stack is electrically coupled to the substrate using a second wire bond. Additionally, the first molding compound encapsulates the first wire bond and the second molding compound encapsulates the second wire bond. Furthermore, a footprint of the second die overlaps a footprint of the first die.Type: ApplicationFiled: April 23, 2019Publication date: October 29, 2020Inventors: Florence PON, Yi XU, James ZHANG, Yuhong CAI, Tyler LEUTEN, William GLENNAN, Hyoung Il KIM
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Publication number: 20200312769Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to an interposer with step features used to electrically couple stacked dies. In embodiments, the step features may appear as a ziggurat shape to one or more sides of the interposer, which may be referred to as a ziggurat interposer. The interposer may have electrical routing disposed within to electrically couple the first face of the one of the step features with a die.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Inventors: Florence PON, Yi Xu
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Publication number: 20200294827Abstract: Embodiments described herein provide a needle dispenser for use in dispensing and collecting an underfill encapsulant under a device on a substrate. In one scenario, the needle dispenser comprises: a reservoir; and a needle coupled to the reservoir. A tip of the needle is comprised of a first material and a body of the needle is comprised of a second material. The first material is more compliant than the second material. An outer surface of the needle is formed from a hydrophobic material and a core of the needle comprises a hydrophilic material. The needle also comprises channels extending along the needle. A solvent flows through at least one of the channels to soak the core. Additionally, openings formed in the needle's outer surface expose the core. The openings enable dispensing or absorbing of the underfill material.Type: ApplicationFiled: March 15, 2019Publication date: September 17, 2020Inventor: Florence PON
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Publication number: 20200235018Abstract: Embodiments described herein are directed to a temporary interconnect for use in testing one or more devices (e.g., one or more dies, inductors, capacitors, etc.) formed in semiconductor package. In one scenario, a temporary interconnect acts an electrical bridge that electrically couples a contact pad on a surface of a substrate and the test pad. Coupling the contact pad and the test pad to each other enables the device(s) coupled the contact pad to be tested. Following testing, the temporary interconnect can be removed or severed so that an electrical break is formed in the conductive path between test pad and the contact pad.Type: ApplicationFiled: January 17, 2019Publication date: July 23, 2020Inventors: Hyoung Il KIM, Yi XU, Florence PON
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Publication number: 20200212009Abstract: Embodiments described herein provide techniques for testing a semiconductor package by using a diode to couple a test pad to a contact pad. In one scenario, a package comprises a die stack comprising one or more dies and a molding compound encapsulating the die stack. In this package, a substrate is over the molding compound. Also, a test pad and a contact pad are on a surface of the substrate. The contact pad is coupled to the die stack. A diode couples the test pad to the contact pad. In one example, the test pad is coupled to a P side of the diode's P-N junction and the contact pad is coupled to an N side of the diode's P-N junction. In operation, current can flow from the test pad through the contact pad (and the die stack), but current cannot flow from the contact pad through the test pad.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Yi XU, Hyoung Il KIM, Florence PON
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Publication number: 20200194344Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate an elastomer coupled to the substrate and a plurality of bondfingers on the elastomer. The substrate, the elastomer and the bondfingers are configured to cooperatively expand and retract.Type: ApplicationFiled: December 13, 2018Publication date: June 18, 2020Inventors: Florence PON, Yi XU, Min-Tih LAI
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Publication number: 20200135616Abstract: Embodiments disclosed herein include electronic packages with chocked flow cooling. In an embodiment, an electronic package may comprise a package substrate, a die electrically and mechanically coupled to the package substrate, and a lid over the die. In an embodiment, the lid has a first opening and a second opening that is opposite from the first opening. In an embodiment, the electronic package may further comprise a coolant plate covering the first opening. In an embodiment, the coolant plate comprises a first surface facing away from the die and a second surface facing the die, and a plurality of vents from the first surface to the second surface. In an embodiment, the first openings of the plurality of vents have a first dimension and second openings of the plurality of vents have a second dimension that is smaller than the first dimension.Type: ApplicationFiled: October 31, 2018Publication date: April 30, 2020Inventors: Mark FORSNES, Yuhong CAI, Florence PON, Yi XU
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Publication number: 20200118941Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of buildup layers, and where each buildup layer has fiber reinforcement. In an embodiment, the electronic package further comprises a reinforcement layer, where the reinforcement layer comprises a buildup layer and fiber reinforcement, and where an orientation of the fibers in the reinforcement layer is different than an orientation of the fibers in the package substrate.Type: ApplicationFiled: October 15, 2018Publication date: April 16, 2020Inventors: Florence PON, Tyler LEUTEN, Maria Angela Damille RAMISO