Patents by Inventor Florent Begon
Florent Begon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11900121Abstract: Aspects of the present disclosure relate to an apparatus comprising prediction circuitry having a plurality of hierarchical prediction units to perform respective hierarchical predictions of instructions for execution, wherein predictions higher in the hierarchy have a higher expected accuracy than predictions lower in the hierarchy. Responsive to a given prediction higher in the hierarchy being different to a corresponding prediction lower in the hierarchy, the corresponding prediction lower in the hierarchy is corrected. A prediction correction metric determination unit determines a prediction correction metric indicative of an incidence of uncorrected predictions performed by the prediction circuitry. Fetch circuitry fetches instructions predicted by at least one of said plurality of hierarchical predictions, and delays said fetching based on the prediction correction metric indicating an incidence of uncorrected predictions below a threshold.Type: GrantFiled: October 14, 2021Date of Patent: February 13, 2024Assignee: Arm LimitedInventors: Guillaume Bolbenes, Florent Begon, Thibaut Elie Lanois, Houdhaifa Bouzguarrou
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Publication number: 20240028516Abstract: A data processing apparatus is provided. Prefetch circuitry generates a prefetch request for a cache line prior to the cache line being explicitly requested. The cache line is predicted to be required for a store operation in the future. Issuing circuitry issues the prefetch request to a memory hierarchy and filter circuitry filters the prefetch request based on at least one other prefetch request made to the cache line, to control whether the prefetch request is issued by the issuing circuitry.Type: ApplicationFiled: December 28, 2022Publication date: January 25, 2024Inventors: Luca MARONCELLI, Cedric Denis Robert AIRAUD, Florent BEGON, Peter Raphael EID
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Publication number: 20230118268Abstract: Aspects of the present disclosure relate to an apparatus comprising prediction circuitry having a plurality of hierarchical prediction units to perform respective hierarchical predictions of instructions for execution, wherein predictions higher in the hierarchy have a higher expected accuracy than predictions lower in the hierarchy. Responsive to a given prediction higher in the hierarchy being different to a corresponding prediction lower in the hierarchy, the corresponding prediction lower in the hierarchy is corrected. A prediction correction metric determination unit determines a prediction correction metric indicative of an incidence of uncorrected predictions performed by the prediction circuitry. Fetch circuitry fetches instructions predicted by at least one of said plurality of hierarchical predictions, and delays said fetching based on the prediction correction metric indicating an incidence of uncorrected predictions below a threshold.Type: ApplicationFiled: October 14, 2021Publication date: April 20, 2023Inventors: Guillaume BOLBENES, Florent BEGON, Thibaut Elie LANOIS, Houdhaifa BOUZGUARROU
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Patent number: 11138119Abstract: There is provided an apparatus that includes storage circuitry. The storage circuitry is made up from a plurality of sets, each of the sets having at least one storage location. Receiving circuitry receives an access request that includes an input address. Lookup circuitry obtains a plurality of candidate sets that correspond with an index part of the input address. The lookup circuitry determines a selected storage location from the candidate sets using an access policy. The access policy causes the lookup circuitry to iterate through the candidate sets to attempt to locate an appropriate storage location. The appropriate storage location is accessed in response to the appropriate storage location being found.Type: GrantFiled: January 15, 2019Date of Patent: October 5, 2021Assignee: Arm LimitedInventors: Damien Guillaume Pierre Payet, Natalya Bondarenko, Florent Begon, Lucas Garcia
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Patent number: 11086781Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations and a hierarchical cache structure. The cache structure comprises a plurality of cache levels to store data for access by the processing circuitry, and includes a highest cache level arranged to receive data requests directly from the processing circuitry.Type: GrantFiled: October 21, 2019Date of Patent: August 10, 2021Assignee: Arm LimitedInventors: Natalya Bondarenko, Florent Begon, Nathanael Premillieu, Pierre Marcel Laurent
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Publication number: 20200125492Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations and a hierarchical cache structure. The cache structure comprises a plurality of cache levels to store data for access by the processing circuitry, and includes a highest cache level arranged to receive data requests directly from the processing circuitry.Type: ApplicationFiled: October 21, 2019Publication date: April 23, 2020Inventors: Natalya BONDARENKO, Florent Begon, Nathanael Premillieu, Pierre Marcel Laurent
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Patent number: 10528355Abstract: An apparatus has processing circuitry, register rename circuitry and control circuitry which selects one of first and second move handling techniques for handling a move instruction specifying a source logical register and a destination logical register. In the first technique, the register rename circuitry maps the destination logical register of the move to the same physical register as the source logical register. In the second technique, the processing circuitry writes a data value read from a physical register corresponding to the source logical register to a different physical register corresponding to the destination local register. The second technique is selected when the move instruction specifies the same source logical register as one of the source and destination logical registers as an earlier move instruction handled according to the first technique, and the register mapping used for that register when handling the earlier move instruction is still current.Type: GrantFiled: December 24, 2015Date of Patent: January 7, 2020Assignee: ARM LimitedInventors: Chris Abernathy, Florent Begon
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Publication number: 20190220414Abstract: There is provided an apparatus that includes storage circuitry. The storage circuitry is made up from a plurality of sets, each of the sets having at least one storage location. Receiving circuitry receives an access request that includes an input address. Lookup circuitry obtains a plurality of candidate sets that correspond with an index part of the input address. The lookup circuitry determines a selected storage location from the candidate sets using an access policy. The access policy causes the lookup circuitry to iterate through the candidate sets to attempt to locate an appropriate storage location. The appropriate storage location is accessed in response to the appropriate storage location being found.Type: ApplicationFiled: January 15, 2019Publication date: July 18, 2019Inventors: Damien Guillaume Pierre PAYET, Natalya BONDARENKO, Florent BEGON, Lucas GARCIA
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Publication number: 20170185410Abstract: An apparatus has processing circuitry, register rename circuitry and control circuitry which selects one of first and second move handling techniques for handling a move instruction specifying a source logical register and a destination logical register. In the first technique, the register rename circuitry maps the destination logical register of the move to the same physical register as the source logical register. In the second technique, the processing circuitry writes a data value read from a physical register corresponding to the source logical register to a different physical register corresponding to the destination local register. The second technique is selected when the move instruction specifies the same source logical register as one of the source and destination logical registers as an earlier move instruction handled according to the first technique, and the register mapping used for that register when handling the earlier move instruction is still current.Type: ApplicationFiled: December 24, 2015Publication date: June 29, 2017Inventors: Chris ABERNATHY, Florent BEGON
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Patent number: 9542194Abstract: A single threaded out-of-order processor 2 includes an architected register file 22 and a speculative register file 20. Speculative register allocation circuitry 24 serves to allocate speculative registers for use in accordance with an allocation sequence and taken from a position determined by a tail point. Read suppression circuitry 30 serves to maintain a boundary pointer corresponding to a position within the allocation sequence such that no speculative register more recently allocated within the allocation sequence than that corresponding to the boundary pointer can have a valid register value. The read suppression circuitry 30 serves to suppress read operations for source operands lying within a read-suppression region delimited by the tail point and the boundary pointer. Separate boundary pointers may be maintained for different types of register values, such as integer register values and floating point register values.Type: GrantFiled: September 10, 2014Date of Patent: January 10, 2017Assignee: ARM LimitedInventors: Chris Abernathy, Florent Begon, Michael Alan Filippo
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Patent number: 9513925Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency.Type: GrantFiled: September 19, 2013Date of Patent: December 6, 2016Assignee: ARM LimitedInventors: Nicolas Chaussade, Florent Begon, Melanie Emanuelle Lucie Teyssier, Remi Teyssier, Jocelyn Francois Orion Jaubert
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Publication number: 20160070576Abstract: A single threaded out-of-order processor 2 includes an architected register file 22 and a speculative register file 20. Speculative register allocation circuitry 24 serves to allocate speculative registers for use in accordance with an allocation sequence and taken from a position determined by a tail point. Read suppression circuitry 30 serves to maintain a boundary pointer corresponding to a position within the allocation sequence such that no speculative register more recently allocated within the allocation sequence than that corresponding to the boundary pointer can have a valid register value. The read suppression circuitry 30 serves to suppress read operations for source operands lying within a read-suppression region delimited by the tail point and the boundary pointer. Separate boundary pointers may be maintained for different types of register values, such as integer register values and floating point register values.Type: ApplicationFiled: September 10, 2014Publication date: March 10, 2016Inventors: Chris ABERNATHY, Florent BEGON, Michael Alan FILIPPO
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Patent number: 9189432Abstract: A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry.Type: GrantFiled: November 15, 2010Date of Patent: November 17, 2015Assignee: ARM LimitedInventors: Melanie Emanuelle Lucie Teyssier, Florent Begon, Jocelyn Francois Orion Jaubert, Nicolas Jean Phillippe Huot
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Patent number: 8769251Abstract: A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided for receiving a block of data containing at least one data value, and for converting each data value from the first endian format to the second endian format. The swizzle circuitry comprises first swizzle circuitry for performing a re-ordering operation on the block of data assuming the at least one data value contained therein is of a first size, in order to produce re-ordered data. Second swizzle circuitry is provided which is responsive to an indication that the at least one data value is of a size different to the first size to perform an additional re-ordering operation on the re-ordered data having regard to the size of the at least one data value in order to convert each data value to the second endian format.Type: GrantFiled: December 13, 2006Date of Patent: July 1, 2014Assignee: ARM LimitedInventors: Philippe Luc, Norbert Bernard Eugéne Lataille, Florent Begon, Nicolas Chaussade
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Publication number: 20140019734Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency.Type: ApplicationFiled: September 19, 2013Publication date: January 16, 2014Applicant: ARM LIMITEDInventors: Nicolas CHAUSSADE, Florent BEGON, Melanie Emanuelle Lucie TEYSSIER, Remi TEYSSIER, Jocelyn Francois Orion JAUBERT
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Patent number: 8578139Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency.Type: GrantFiled: August 5, 2010Date of Patent: November 5, 2013Assignee: ARM LimitedInventors: Nicolas Chaussade, Florent Begon, Mélanie Emanuelle Lucie Teyssier, Rémi Teyssier, Jocelyn Francois Orion Jaubert
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Patent number: 8458532Abstract: A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data values stored within the data caches 12, 14, 16, 18. The snoop control unit 20 incorporates a TAG memory 22. If an error is detected within an entry of the TAG memory 22, then a hit operation is forced to the corresponding storage location one or more of the data caches 12, 14, 16, 18.Type: GrantFiled: October 27, 2010Date of Patent: June 4, 2013Assignee: ARM LimitedInventors: Jocelyn Francois Orion Jaubert, Florent Begon, Melanie Emanuelle Lucie Teyssier
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Patent number: 8352794Abstract: Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal.Type: GrantFiled: November 19, 2009Date of Patent: January 8, 2013Assignee: ARM LimitedInventors: Remi Teyssier, Florent Begon, Jocelyn Francois Orion Jaubert, Cédric Denis Robert Airaud
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Publication number: 20120124300Abstract: A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Applicant: ARM LIMITEDInventors: Melanie Emanuelle Lucie Teyssier, Florent Begon, Jocelyn Francois Orion Jaubert, Nicolas Jean Phillippe Huot
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Publication number: 20120110396Abstract: A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data values stored within the data caches 12, 14, 16, 18. The snoop control unit 20 incorporates a TAG memory 22. If an error is detected within an entry of the TAG memory 22, then a hit operation is forced to the corresponding storage location one or more of the data caches 12, 14, 16, 18.Type: ApplicationFiled: October 27, 2010Publication date: May 3, 2012Applicant: ARM LIMITEDInventors: Jocelyn Francois Orion Jaubert, Florent Begon, Melanie Emanuelle Lucie Teyssier