Abstract: The present disclosure relates to a method of storing, by a load and store circuit or other processing means, a variable precision floating point value to a memory address of a memory, the method comprising: reducing the bit length of the variable precision floating point value to no more than a size limit, and storing the variable precision floating point value to one of a plurality of storage zones in the memory, each of the plurality of storage zones having a storage space equal to or greater than the size limit (MBB).

Abstract: The present disclosure relates to a method of storing, by a load and store circuit or other processing means, a variable precision floating point value to a memory address of a memory, the method comprising: reducing the bit length of the variable precision floating point value to no more than a size limit, and storing the variable precision floating point value to one of a plurality of storage zones in the memory, each of the plurality of storage zones having a storage space equal to or greater than the size limit (MBB).

Abstract: A compression method includes simplifying a mesh that represents a textured 3D-object by replacing polygons in the mesh with new ones that have broader faces. The method includes identifying adjacent polygons with different textures and adding vertices at the same positions as two vertices in the polygons. This creates two new edges and an intermediate polygon interposed between the two adjacent polygons. The new edges have zero length and the new polygon has zero area.

Abstract: A compression method includes simplifying a mesh that represents a textured 3D-object by replacing polygons in the mesh with new ones that have broader faces. The method includes identifying adjacent polygons with different textures and adding vertices at the same positions as two vertices in the polygons. This creates two new edges and an intermediate polygon interposed between the two adjacent polygons. The new edges have zero length and the new polygon has zero area.

Abstract: An electrical stimulation system including: a mechanism generating at least one electrical signal to be applied to a biological tissue that is to stimulated and measuring a response of the biological tissue to each electrical signal; a calculation mechanism estimating, based on each electrical signal and on a corresponding response of the biological tissue, at least one parameter of an electrical model of the biological tissue and its interface with the electrical stimulation system and determining, using the model, at least one parameter of a stimulation pulse to be applied to the biological tissue by the electrical stimulation system; and a mechanism generating a stimulation pulse to be applied to the biological tissue.

Abstract: A circuit for calculating the fused sum of an addend and product of two multiplication operands, the addend and multiplication operands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent is provided. The multiplication operands are in a lower precision format than the addend, with q>2p, where p and q are the mantissa size of the multiplication operand and addend precision formats. The circuit includes a p-bit multiplier receiving the mantissas of the multiplication operands; a shift circuit aligning the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplication operands; and an adder processing q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa.

Abstract: The present invention relates to a method for forming a crystallized silicon layer made up of grains having an average size of no less than 20 ?m, including at least the steps that comprise: (1) providing a layer of silicon to be (re)crystallized, the average grain size of which is less than 10 ?m; (2) placing said layer of silicon to be (re)crystallized in contact with a liquid composition at least partially made up of a metal solvent; and (3) exposing the assembly to a thermal treatment suitable for (re)crystallizing said layer of silicon with the expected grain size, characterized in that said thermal treatment includes heating the assembly made up of the layer of silicon in contact with said liquid composition to a temperature that is lower than 1410° C. and at least equal to the eutectic temperature in the solvent-silicon phase diagram.

Abstract: The present invention relates to a method for forming a crystallised silicon layer made up of grains having an average size of no less than 20 ?m, including at least the steps that comprise: (1) providing a layer of silicon to be (re)crystallised, the average grain size of which is less than 10 ?m; (2) placing said layer of silicon to be (re)crystallised in contact with a liquid composition at least partially made up of a metal solvent; and (3) exposing the assembly to a thermal treatment suitable for (re)crystallising said layer of silicon with the expected grain size, characterised in that said thermal treatment includes heating the assembly made up of the layer of silicon in contact with said liquid composition to a temperature that is lower than 1410° C. and at least equal to the eutectic temperature in the solvent-silicon phase diagram.

Abstract: A circuit for calculating the fused sum of an addend and product of two multiplicands, the addend and multiplicands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent is provided. The multiplicands are in a lower precision format than the addend, with q>2p, where p and q are respectively the mantissa size of the multiplicand precision format and the addend precision format. The circuit includes a p-bit multiplier receiving the mantissas of the multiplicands; a shift circuit that aligns the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplicands; and an adder that processes q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa.