Patents by Inventor Florent Dupont De Dinechin

Florent Dupont De Dinechin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200285468
    Abstract: The present disclosure relates to a method of storing, by a load and store circuit or other processing means, a variable precision floating point value to a memory address of a memory, the method comprising: reducing the bit length of the variable precision floating point value to no more than a size limit, and storing the variable precision floating point value to one of a plurality of storage zones in the memory, each of the plurality of storage zones having a storage space equal to or greater than the size limit (MBB).
    Type: Application
    Filed: March 6, 2020
    Publication date: September 10, 2020
    Inventors: Andrea BOCCO, Florent DUPONT DE DINECHIN, Yves DURAND
  • Patent number: 9367287
    Abstract: A circuit for calculating the fused sum of an addend and product of two multiplication operands, the addend and multiplication operands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent is provided. The multiplication operands are in a lower precision format than the addend, with q>2p, where p and q are the mantissa size of the multiplication operand and addend precision formats. The circuit includes a p-bit multiplier receiving the mantissas of the multiplication operands; a shift circuit aligning the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplication operands; and an adder processing q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: June 14, 2016
    Assignee: KALRAY
    Inventors: Florent Dupont De Dinechin, Nicolas Brunie, Benoit Dupont De Dinechin
  • Publication number: 20140089371
    Abstract: A circuit for calculating the fused sum of an addend and product of two multiplicands, the addend and multiplicands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent is provided. The multiplicands are in a lower precision format than the addend, with q>2p, where p and q are respectively the mantissa size of the multiplicand precision format and the addend precision format. The circuit includes a p-bit multiplier receiving the mantissas of the multiplicands; a shift circuit that aligns the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplicands; and an adder that processes q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa.
    Type: Application
    Filed: April 19, 2012
    Publication date: March 27, 2014
    Applicant: KALRAY
    Inventors: Florent Dupont De Dinechin, Nicolas Brunie, Benoit Dupont De Dinechin