Patents by Inventor Florent RAVAUX

Florent RAVAUX has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • STRESS LAYOUT OPTIMIZATION FOR DEVICE PERFORMANCE
    Publication number: 20230238439
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.
    Type: Application
    Filed: March 28, 2023
    Publication date: July 27, 2023
    Inventors: Dirk UTESS, Zhixing ZHAO, Dominik M. KLEIMAIER, Irfan A. SAADAT, Florent RAVAUX
  • Stress layout optimization for device performance
    Patent number: 11664432
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 30, 2023
    Assignees: GLOBALFOUNDRIES U.S. INC., KHALIFA UNIVERSITY
    Inventors: Dirk Utess, Zhixing Zhao, Dominik M. Kleimaier, Irfan A. Saadat, Florent Ravaux
  • STRESS LAYOUT OPTIMIZATION FOR DEVICE PERFORMANCE
    Publication number: 20210066463
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Dirk UTESS, Zhixing ZHAO, Dominik M. KLEIMAIER, Irfan A. SAADAT, Florent RAVAUX