Patents by Inventor Florentin Dartu
Florentin Dartu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240143880Abstract: A method includes determining a first timing of a transition sequence of a signal on a first path of an integrated circuit (IC) design, the first timing being based on an IC design signoff voltage, determining a second timing of the transition sequence of the signal on the first path, the second timing being based on the signoff voltage and a first voltage drop along the first path, calculating a first path derating factor based on a timing gap between the first and second timings of the transition sequence, and using the first path derating factor to evaluate the IC design.Type: ApplicationFiled: January 27, 2023Publication date: May 2, 2024Inventors: Yu-Wen LIN, Bogdan TUTUIANU, Florentin DARTU, Wei-Chih HSIEH, Osamu TAKAHASHI
-
Publication number: 20230385512Abstract: A method (of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including a subset of transistor-to-well-edge-influenced (TWEI) cells, each TWEI cell including one or more transistors in one or more corresponding wells) includes generating a netlist which represents the subset, the generating a netlist including: In some embodiments, for each TWEI cell represented in the netlist, and for a given transistor in a given well in a given cell, expanding the netlist to include one or more proximity-effect-inducer (PEI) parameters, each PEI parameter being related to an intra-cell physical proximity of the given transistor to an edge of the given well (given well-edge).Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Yen-Pin CHEN, Florentin DARTU, Wei-Chih HSIEH, Tzu-Hen LIN, Chung-Hsing WANG
-
Publication number: 20220245318Abstract: For a method of manufacturing a semiconductor device, a corresponding layout diagram is stored on a non-transitory computer-readable medium, the layout diagram being arranged relative to first and second perpendicular directions, the layout diagram including cells such that, for a subset of the cells, each subject one of the cells (subject cell) in the subset has a neighborhood including first and second neighbor cells on corresponding first and second sides of the subject cell relative to the first direction. The method includes: for each subject cell in the subset, generating a sidefile which represents neighborhood-specific proximity-effect information.Type: ApplicationFiled: June 22, 2021Publication date: August 4, 2022Inventors: Yen-Pin CHEN, Florentin DARTU, Wei-Chih HSIEH, Tzu-Hen LIN, Chung-Hsing WANG
-
Patent number: 11176305Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, the information including a mean of slacks and a sigma of slacks of each of the paths; determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma; dividing the paths into groups based on SM values, an SM value of a path in one of the groups being different from that of a path in another one of the groups; and determining a yield requirement that indicates the maximum number of paths allowable in each group in order to achieve a predetermined yield.Type: GrantFiled: May 19, 2020Date of Patent: November 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yen-Pin Chen, Tzu-Hen Lin, Tai-Yu Cheng, Florentin Dartu, Chung-Hsing Wang
-
Publication number: 20200279068Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, the information including a mean of slacks and a sigma of slacks of each of the paths; determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma; dividing the paths into groups based on SM values, an SM value of a path in one of the groups being different from that of a path in another one of the groups; and determining a yield requirement that indicates the maximum number of paths allowable in each group in order to achieve a predetermined yield.Type: ApplicationFiled: May 19, 2020Publication date: September 3, 2020Inventors: YEN-PIN CHEN, TZU-HEN LIN, TAI-YU CHENG, FLORENTIN DARTU, CHUNG-HSING WANG
-
Patent number: 10678989Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, wherein the information includes a mean of slacks and a sigma of slacks of each of the paths, determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma, and determining that a first path of the paths is more critical than a second path of the paths, an SM value of the first path being smaller than that of the second path.Type: GrantFiled: January 18, 2018Date of Patent: June 9, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yen-Pin Chen, Tzu-Hen Lin, Tai-Yu Cheng, Florentin Dartu, Chung-Hsing Wang
-
Publication number: 20180247007Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, wherein the information includes a mean of slacks and a sigma of slacks of each of the paths, determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma, and determining that a first path of the paths is more critical than a second path of the paths, an SM value of the first path being smaller than that of the second path.Type: ApplicationFiled: January 18, 2018Publication date: August 30, 2018Inventors: YEN-PIN CHEN, TZU-HEN LIN, TAI-YU CHENG, FLORENTIN DARTU, CHUNG-HSING WANG
-
Patent number: 8701075Abstract: A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block.Type: GrantFiled: April 8, 2013Date of Patent: April 15, 2014Assignee: Synopsys, Inc.Inventors: Florentin Dartu, Patrick D. Fortner, Kayhan Kucukcakar, Qiuyang Wu
-
Patent number: 8443328Abstract: A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block.Type: GrantFiled: June 14, 2010Date of Patent: May 14, 2013Assignee: Synopsys, Inc.Inventors: Florentin Dartu, Patrick D. Fortner, Kayhan Kucukcakar, Qiuyang Wu
-
Publication number: 20110307850Abstract: A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block.Type: ApplicationFiled: June 14, 2010Publication date: December 15, 2011Applicant: SYNOPSYS, INC.Inventors: Florentin Dartu, Patrick D. Fortner, Kayhan Kucukcakar, Qiuyang Wu
-
Patent number: 8042010Abstract: One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a set of blocks that are clocked by an independent clock source, and integrates an error signal propagation circuit between the set of blocks. For a respective block, the system determines a set of internal registers that are to be implemented as double data sampling registers, and replaces the determined set of internal registers with double data sampling registers, wherein a given double data sampling register is configured to generate an error signal when it detects a timing error. Then, the system integrates a two-phase error correction circuit into the respective block, wherein when notified of a timing error by a double data sampling register, the two-phase error correction circuit is configured to stall registers in the respective block.Type: GrantFiled: October 22, 2008Date of Patent: October 18, 2011Assignee: Synopsys, Inc.Inventors: Florentin Dartu, Narendra V. Shenoy
-
Publication number: 20100097107Abstract: One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a set of blocks that are clocked by an independent clock source, and integrates an error signal propagation circuit between the set of blocks. For a respective block, the system determines a set of internal registers that are to be implemented as double data sampling registers, and replaces the determined set of internal registers with double data sampling registers, wherein a given double data sampling register is configured to generate an error signal when it detects a timing error. Then, the system integrates a two-phase error correction circuit into the respective block, wherein when notified of a timing error by a double data sampling register, the two-phase error correction circuit is configured to stall registers in the respective block.Type: ApplicationFiled: October 22, 2008Publication date: April 22, 2010Applicant: SYNOPSYS, INC.Inventors: Florentin Dartu, Narendra V. Shenoy
-
Publication number: 20030011383Abstract: A method and apparatus for frequency domain noise analysis that uses moment matching techniques and reciprocity to provide efficient noise analysis without the need for one analysis per attacker and without resorting to pruning techniques and their concommitant error.Type: ApplicationFiled: June 27, 2001Publication date: January 16, 2003Inventors: Noel Menezes, Florentin Dartu
-
Patent number: 6498498Abstract: A method and apparatus for frequency domain noise analysis that uses moment matching techniques and reciprocity to provide efficient noise analysis without the need for one analysis per attacker and without resorting to pruning techniques and their concommitant error.Type: GrantFiled: June 27, 2001Date of Patent: December 24, 2002Assignee: Intel CorporationInventors: Noel Menezes, Florentin Dartu