Abstract: A technique for handling cache-inhibited operations in a data processing system includes receiving, at a replicated bus unit, a cache-inhibited (CI) operation. The replicated bus unit determines whether an address associated with the CI operation matches an address for the replicated bus unit and whether a source indicated by the CI operation is associated with the replicated bus unit. In response to the address associated with the CI operation matching the address for the replicated bus unit and the source indicated by the CI operation being associated with the replicated bus unit, the replicated bus unit processes the CI operation. In response to the address associated with the CI operation not matching the address for the replicated bus unit or the source indicated by the CI operation not being associated with the replicated bus unit, the replicated bus unit ignores the CI operation.

Abstract: A technique for handling cache-inhibited operations in a data processing system includes receiving, at a replicated bus unit, a cache-inhibited (CI) operation. The replicated bus unit determines whether an address associated with the CI operation matches an address for the replicated bus unit and whether a source indicated by the CI operation is associated with the replicated bus unit. In response to the address associated with the CI operation matching the address for the replicated bus unit and the source indicated by the CI operation being associated with the replicated bus unit, the replicated bus unit processes the CI operation. In response to the address associated with the CI operation not matching the address for the replicated bus unit or the source indicated by the CI operation not being associated with the replicated bus unit, the replicated bus unit ignores the CI operation.

Abstract: An I/O controller, coupled to a processing unit and to a memory, includes an I/O link interface configured to receive data packets having virtual addresses; an address translation unit having an address translator to translate received virtual addresses into real addresses by translation control entries and a cache allocated to the address translator to cache a number of the translation control entries; an I/O packet processing unit for checking the data packets received at the I/O link interface and for forwarding the checked data packets to the address translation unit; and a prefetcher to forward address translation prefetch information from a data packet received to the address translation unit; the address translator configured to fetch the translation control entry for the data packet by the address translation prefetch information from the allocated cache or, if the translation control entry is not available in the allocated cache, from the memory.

Abstract: A method for directing cache injection based on actual system load may include providing a snooping-based fabric having two or more bus-coupled units. At least one of the bus-coupled units may be configured as an injection unit for directing cache injection. A snoop request may be transmitted from the injection unit to one or more destination units of the other bus-coupled unit. The snoop request may include an identification value having a function identifier. The function identifier may identify a destination function for the cache injection, where the destination function is configured to run on the destination unit. A snoop response may be transmitted from the destination unit to the injection unit in response to the snoop request. The snoop response may include a function response value indicating whether the function identifier matches a function indication of a snoop register for the destination unit.

Abstract: A method for managing objects stored in a cache memory of a processing unit. The cache memory includes a set of entries corresponding to an object. The method includes: checking, for each entry of at least a subset of entries of the set of entries of the cache memory, whether an object corresponding to each entry includes one or more references to one or more other objects stored in the cache memory and storing the references; determining among the objects stored in the cache memory, which objects are not referenced by other objects, based on the stored references; marking entries as checked to distinguish entries corresponding to objects determined as being not referenced from other entries of the checked entries, and casting out, according to the marking, entries corresponding to objects determined as being not referenced.

Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes N machines configured to handle requests from the requesting interconnect and for handling allocated responses from the serving interconnect, wherein each of the N machines has an allocated local count; a tracking entity configured to track priorities of the N machines for issuing received requests to the serving interconnect and for issuing received responses to the requesting interconnect based on the N local counts; a first arbiter configured to arbitrate the received requests to be issued to the serving interconnect based on the tracked priorities; and a second arbiter configured to arbitrate the received responses to be issued to the requesting interconnect based on the tracked priorities.

Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes a first interface configured to receive a read request and a number of dependent write requests that the read request depends on from the requesting interconnect; and an issuer configured to issue the received number of dependent write requests to the serving interconnect and for issuing the received read request to the serving interconnect after issuing the number of dependent write requests and before receiving write acknowledgments for the issued dependent write requests from the serving interconnect.

Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes N machines configured to handle requests from the requesting interconnect and for handling allocated responses from the serving interconnect, wherein each of the N machines has an allocated local count; a tracking entity configured to track priorities of the N machines for issuing received requests to the serving interconnect and for issuing received responses to the requesting interconnect based on the N local counts; a first arbiter configured to arbitrate the received requests to be issued to the serving interconnect based on the tracked priorities; and a second arbiter configured to arbitrate the received responses to be issued to the requesting interconnect based on the tracked priorities.

Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes a first interface configured to receive a read request and a number of dependent write requests that the read request depends on from the requesting interconnect; and an issuer configured to issue the received number of dependent write requests to the serving interconnect and for issuing the received read request to the serving interconnect after issuing the number of dependent write requests and before receiving write acknowledgments for the issued dependent write requests from the serving interconnect.

Abstract: An I/O controller, coupled to a processing unit and to a memory, includes an I/O link interface configured to receive data packets having virtual addresses; an address translation unit having an address translator to translate received virtual addresses into real addresses by translation control entries and a cache allocated to the address translator to cache a number of the translation control entries; an I/O packet processing unit for checking the data packets received at the I/O link interface and for forwarding the checked data packets to the address translation unit; and a prefetcher to forward address translation prefetch information from a data packet received to the address translation unit; the address translator configured to fetch the translation control entry for the data packet by the address translation prefetch information from the allocated cache or, if the translation control entry is not available in the allocated cache, from the memory.

Abstract: An I/O controller, coupled to a processing unit and to a memory, includes an I/O link interface configured to receive data packets having virtual addresses; an address translation unit having an address translator to translate received virtual addresses into real addresses by translation control entries and a cache allocated to the address translator to cache a number of the translation control entries; an I/O packet processing unit for checking the data packets received at the I/O link interface and for forwarding the checked data packets to the address translation unit; and a prefetcher to forward address translation prefetch information from a data packet received to the address translation unit; the address translator configured to fetch the translation control entry for the data packet by the address translation prefetch information from the allocated cache or, if the translation control entry is not available in the allocated cache, from the memory.

Abstract: An address translation unit for Remote Direct Memory Access (RDMA) of a memory of a processor is provided. The address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.

Abstract: A method for Remote Direct Memory Access (RDMA) of a memory of a processor. An address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.

Abstract: A device for multi-stage translation of prefetch requests includes a prefetch queue for providing queued prefetch requests, each of the queued prefetch requests including N different control entries; N serial-connected translation stages for the translation of N control entries of one of the queued prefetch requests into a translated prefetch request, wherein a translation in a i-th translation stage is dependent on a translation in a (i?1)-th translation stage, i ? [1, . . . ,N]; and a prefetch issuer which is configured to control an index for each of the N different control entries in the prefetch queue and to issue a prefetch of the indexed control entry of the N different control entries for the highest non-stalled translation stage.

Abstract: A mechanism is provided for scheduling virtual interfaces having at least one virtual interface scheduler, a virtual interface context cache and a pipeline with a number of processing units. The virtual interface scheduler is configured to send a lock request for a respective virtual interface to the virtual interface context cache. The virtual interface context cache is configured to lock a virtual interface context of the respective virtual interface and to send a lock token to the virtual interface scheduler in dependence on said lock request. The virtual interface context cache configured to hold a current lock token for the respective virtual interface context and to unlock the virtual interface context, if a lock token of an unlock request received from the pipeline matches the held current lock token.

Abstract: A mechanism is provided for scheduling virtual interfaces having at least one virtual interface scheduler, a virtual interface context cache and a pipeline with a number of processing units. The virtual interface scheduler is configured to send a lock request for a respective virtual interface to the virtual interface context cache. The virtual interface context cache is configured to lock a virtual interface context of the respective virtual interface and to send a lock token to the virtual interface scheduler in dependence on said lock request. The virtual interface context cache configured to hold a current lock token for the respective virtual interface context and to unlock the virtual interface context, if a lock token of an unlock request received from the pipeline matches the held current lock token.

Abstract: A method for Remote Direct Memory Access (RDMA) of a memory of a processor. An address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.

Abstract: An address translation unit for Remote Direct Memory Access (RDMA) of a memory of a processor is provided. The address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.

Abstract: A mechanism is provided for scheduling virtual interfaces having at least one virtual interface scheduler, a virtual interface context cache and a pipeline with a number of processing units. The virtual interface scheduler is configured to send a lock request for a respective virtual interface to the virtual interface context cache. The virtual interface context cache is configured to lock a virtual interface context of the respective virtual interface and to send a lock token to the virtual interface scheduler in dependence on said lock request. The virtual interface context cache configured to hold a current lock token for the respective virtual interface context and to unlock the virtual interface context, if a lock token of an unlock request received from the pipeline matches the held current lock token.

Abstract: A system for I/O controller-processor interconnect coupling supporting a push-pull DMA read operation, in one aspect, may comprise a processor interconnect comprising a plurality of caches and memory subsystems and an I/O controller coupled with the processor interconnect. The I/O controller may comprise a plurality of DMA read request queues, a DMA read slot pool comprising a plurality of DMA read slots, and an expander logic determining a priority of requests in said request queues.