Abstract: A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.

Abstract: Embodiments of the invention provide a method, system, and computer program product for cache-line based notification. An embodiment of the method comprises injecting a cache-line including notification information into a cache of a processing unit, marking the cache-line as having the notification information, and using the notification information to notify a processing thread of the presence of the cache-line in the cache. In an embodiment, the cache-line identifies a thread affiliation. In an embodiment, a multitude of threads operate in the processing unit, and the using includes notifying a plurality of these threads of the presence of the cache-line in the cache, and analyzing the cache-line to identify this plurality of threads. The cache may include a plurality of cache-lines, each of which includes a notification, and the processing unit thread uses these notifications to form a linked list of at least some of the cache-lines.

Abstract: A system and method employing the system for pushing work request associated contexts into a computer device includes issuing a request to a device in a computer system. Context data is fetched from a data storage device for the device. Context is determined for specified data requests, and context misses in the device are predicted. The system and method then initiates a context push and pushes the context into the device using a controller when a context miss is detected. Thereby, reducing the context miss latency time or delay in retrieving context data.

Abstract: A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.

Abstract: A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.

Abstract: A memory device comprising a cache memory with a predetermined amount of cache sets, each cache set comprising a predetermined amount of cache lines. Each cache line is operable to indicate a cache data injection into the particular cache line triggered by a bus-actor.

Abstract: A system and method employing the system for pushing work request associated contexts into a computer device includes issuing a request to a device in a computer system. Context data is fetched from a data storage device for the device. Context is determined for specified data requests, and context misses in the device are predicted. The system and method then initiates a context push and pushes the context into the device using a controller when a context miss is detected. Thereby, reducing the context miss latency time or delay in retrieving context data.

Abstract: Embodiments of the invention provide a method, system, and computer program product for cache-line based notification. An embodiment of the method comprises injecting a cache-line including notification information into a cache of a processing unit, marking the cache-line as having the notification information, and using the notification information to notify a processing thread of the presence of the cache-line in the cache. In an embodiment, the cache-line identifies a thread affiliation. In an embodiment, a multitude of threads operate in the processing unit, and the using includes notifying a plurality of these threads of the presence of the cache-line in the cache, and analyzing the cache-line to identify this plurality of threads. The cache may include a plurality of cache-lines, each of which includes a notification, and the processing unit thread uses these notifications to form a linked list of at least some of the cache-lines.

Abstract: A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.