Patents by Inventor Florian Bieck
Florian Bieck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9929018Abstract: A semiconductor wafer (12) with a thinned central portion (2) has a first side (3) and a second side (4) and at least one reinforcement structure for increasing the radial bending resistance of the semiconductor wafer (12). The reinforcement structure provides at least one passage (10) for a fluid flow between an inner face (9) of said one reinforcement structure towards an outer face (8) of the reinforcement structure. The passages (10) are manufactured in a z-direction coming from above the semiconductor wafer (12) in a direction which is essentially perpendicular to the surface, e.g. to the first side (3), of the semiconductor wafer (12).Type: GrantFiled: February 28, 2015Date of Patent: March 27, 2018Assignee: DISCO CORPORATIONInventors: Florian Bieck, Carolinda Sukmadevi Asfhandy, Sven-Manfred Spiller
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Patent number: 9245765Abstract: Implementations and techniques for applying a film to a semiconductor wafer and for processing a semiconductor wafer are generally disclosed.Type: GrantFiled: October 14, 2010Date of Patent: January 26, 2016Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Florian Bieck
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Patent number: 9207276Abstract: A method for testing a semiconductor wafer comprises providing a semiconductor wafer. The semiconductor wafer comprises a protruding annular rim, a first redistribution structure disposed on the front side of the semiconductor wafer, a second redistribution structure disposed on the rear side of the semiconductor wafer within the protruding annular rim and a plurality of vias extending from the front side to the rear side. A first probe is contacted to the first redistribution structure on the front side and a second probe is contacted to the second redistribution structure on the rear side. The first probe is in contact with the first redistribution structure and the second probe is in contact with the second redistribution structure at the same time.Type: GrantFiled: November 26, 2009Date of Patent: December 8, 2015Assignee: DISCO CORPORATIONInventor: Florian Bieck
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Publication number: 20150235900Abstract: A semiconductor wafer (12) with a thinned central portion (2) has a first side (3) and a second side (4) and at least one reinforcement structure for increasing the radial bending resistance of the semiconductor wafer (12). The reinforcement structure provides at least one passage (10) for a fluid flow between an inner face (9) of said one reinforcement structure towards an outer face (8) of the reinforcement structure. The passages (10) are manufactured in a z-direction coming from above the semiconductor wafer (12) in a direction which is essentially perpendicular to the surface, e.g. to the first side (3), of the semiconductor wafer (12).Type: ApplicationFiled: February 28, 2015Publication date: August 20, 2015Inventors: Florian Bieck, Carolinda Sukmadevi Asfhandy, Sven-Manfred Spiller
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Patent number: 9076779Abstract: The present disclosure includes novel techniques to provide wafer level fan-outs in electronic circuit packages housing one or more circuit devices, at least one of which has input and/or output nodes disposed on opposite facings.Type: GrantFiled: April 3, 2012Date of Patent: July 7, 2015Assignee: International Rectifier CorporationInventors: Florian Bieck, Robert J. Montgomery
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Patent number: 9063407Abstract: A photolithography mask for a semiconductor wafer. The mask includes a protrusion section that protrudes from a handling section of the mask. An outer shape of the handling section enables handling by a mask aligner device. The protrusion includes a face surface provided at a level which is different from a face surface area of the handling section.Type: GrantFiled: August 10, 2011Date of Patent: June 23, 2015Assignee: DISCO CORPORATIONInventors: Florian Bieck, Sven Spiller
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Patent number: 9000512Abstract: An assembler receives a circuit device and a mass of conductive material such as a diode, metal material, etc. The assembler bonds a first facing of a circuit device to a substrate. Adjacent to the circuit device, the assembler bonds a first facing of the mass of conductive material to the substrate. The assembler applies an overmold layer of insulation material over the substrate adjacent the circuit device and the mass of conductive material. Subsequent to applying the overmold layer of insulation material, the assembler provides a conductive link between a second facing of the circuit device and a second facing of the mass of conductive material.Type: GrantFiled: February 28, 2013Date of Patent: April 7, 2015Assignee: International Rectifier CorporationInventors: Florian Bieck, Robert J. Montgomery
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Publication number: 20130260291Abstract: A photolithography mask for a semiconductor wafer. The mask includes a protrusion section that protrudes from a handling section of the mask. An outer shape of the handling section enables handling by a mask aligner device. The protrusion includes a face surface provided at a level which is different from a face surface area of the handling section.Type: ApplicationFiled: August 10, 2011Publication date: October 3, 2013Applicant: DISCO CORPORATIONInventors: Florian Bieck, Sven Spiller
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Publication number: 20130137259Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.Type: ApplicationFiled: January 8, 2013Publication date: May 30, 2013Applicant: WAFER-LEVEL PACKAGING PORTFOLIO LLCInventors: Florian Bieck, Jeurgen Leib
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Patent number: 8349707Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.Type: GrantFiled: September 30, 2010Date of Patent: January 8, 2013Assignee: Wafer-Level Packaging Portfolio LLCInventors: Dipl.-Ing. Florian Bieck, Jürgen Leib
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Publication number: 20120299610Abstract: A method for testing a semiconductor wafer comprises providing a semiconductor wafer. The semiconductor wafer comprises a protruding annular rim, a first redistribution structure disposed on the front side of the semiconductor wafer, a second redistribution structure disposed on the rear side of the semiconductor wafer within the protruding annular rim and a plurality of vias extending from the front side to the rear side. A first probe is contacted to the first redistribution structure on the front side and a second probe is contacted to the second redistribution structure on the rear side. The first probe is in contact with the first redistribution structure and the second probe is in contact with the second redistribution structure at the same time.Type: ApplicationFiled: November 26, 2009Publication date: November 29, 2012Applicant: DOUBLECHECK SEMICONDUCTORS PTE. LTD.Inventor: Florian Bieck
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Publication number: 20120168940Abstract: Implementations and techniques for applying a film to a semiconductor wafer and for processing a semiconductor wafer are generally disclosed.Type: ApplicationFiled: October 14, 2010Publication date: July 5, 2012Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Florian Bieck
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Patent number: 8114304Abstract: In order to achieve an integration of functional structures into the housing of electronic components, provision is made of a method for producing an electronic component comprising at least one semiconductor element having at least one sensor-technologically active and/or emitting device on at least one side, the method comprising the following steps: provision of at least one die on a wafer, production of at least one patterned support having at least one structure which is functional for the sensor-technologically active and/or emitting device, joining together of the wafer with the at least one support, so that that side of the die which has the sensor-technologically active and/or emitting device faces the support, separation of the die.Type: GrantFiled: November 22, 2006Date of Patent: February 14, 2012Assignee: Wafer-Level Packaging Portfolio LLCInventors: Jürgen Leib, Florian Bieck
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Publication number: 20110260296Abstract: A semiconductor wafer (12) with a thinned central portion (2) has a first side (3) and a second side (4) and at least one reinforcement structure for increasing the radial bending resistance of the semiconductor wafer (12). The reinforcement structure provides at least one passage (10) for a fluid flow between an inner face (9) of said one reinforcement structure towards an outer face (8) of the reinforcement structure. The passages (10) are manufactured in a z-direction coming from above the semiconductor wafer (12) in a direction which is essentially perpendicular to the surface, e.g. to the first side (3), of the semiconductor wafer (12).Type: ApplicationFiled: November 23, 2009Publication date: October 27, 2011Inventors: Florian Bieck, Carolinda Sukmadevi Asfhandy, Sven-Manfred Spiller
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Patent number: 7880179Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.Type: GrantFiled: November 20, 2009Date of Patent: February 1, 2011Assignee: Wafer-Level Packaging Portfolio LLCInventors: Dipl.-Ing. Florian Bieck, Jürgen Leib
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Publication number: 20110021002Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.Type: ApplicationFiled: September 30, 2010Publication date: January 27, 2011Inventors: Dipl.-Ing. Florian Bieck, Jürgen Leib
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Patent number: 7825029Abstract: A method for the patterned coating of a substrate with at least one surface is provided. The method is suitable for the rapid and inexpensive production of precise patterns. The method includes the steps of: producing at least one negatively patterned first coating on the at least one surface, depositing at least one second layer, which includes a material with a vitreous structure, on the surface, and at least partially removing the first coating.Type: GrantFiled: April 15, 2003Date of Patent: November 2, 2010Assignee: Schott AGInventors: Jurgen Leib, Florian Bieck, Dietrich Mund
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Patent number: 7821106Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.Type: GrantFiled: March 4, 2008Date of Patent: October 26, 2010Assignee: Schott AGInventors: Florian Bieck, Jürgen Leib
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Patent number: 7700957Abstract: The invention proposes a process for producing electrical contact connections for at least one component which is integrated in a substrate material, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.Type: GrantFiled: September 22, 2004Date of Patent: April 20, 2010Assignee: Schott AGInventors: Florian Bieck, Jürgen Leib
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Publication number: 20100065883Abstract: A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.Type: ApplicationFiled: November 20, 2009Publication date: March 18, 2010Inventors: Dipl.-Ing. Florian Bieck, Jurgen Leib