Patents by Inventor Florian Bogenberger
Florian Bogenberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100213964Abstract: A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit.Type: ApplicationFiled: September 25, 2007Publication date: August 26, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Florian Bogenberger, Leos Chalupa
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Publication number: 20100107025Abstract: A system for testing a logic circuit which has two or more test routine modules. Each module contains a set of instructions which is executable by (a part of) the logic circuit. The set forms a test routine for performing a self-test by the part of the logic circuit. The self-test includes the part of the logic circuit testing itself for faulty behaviour, and the part of the logic circuit determining a self-test result of the testing. The system includes a test module which can execute a test application which subjects the logic circuit to a test by performing the self-test on at least a part of the logic circuit by causes the part of the logic circuit to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine.Type: ApplicationFiled: February 16, 2007Publication date: April 29, 2010Applicant: Freescale Semiconductor, IncInventors: Oleksandr Sakada, Florian Bogenberger
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Publication number: 20100073043Abstract: A data communication network may, include a first sub-network and a second sub-network. The first sub-network may include two or more two master clocks, and a synchronisation system connected to the master clocks. The synchronisation system may, for determine a time-base for the master clocks and control the master clocks based on the determined time-base. The first sub-network may include one or more slave synchronisation data source for generating slave clock synchronisation data derived from time information of the master clocks. The second sub-network may include one or more slave clocks and a slave clock time-base controller connected to the slave synchronisation data source. The time-base controller may receive the slave clock synchronisation data and control one or more of the one or more slave clocks in accordance with the slave clock synchronisation data.Type: ApplicationFiled: October 31, 2006Publication date: March 25, 2010Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Florian Bogenberger, Mathias Rausch
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Publication number: 20100030939Abstract: An request controller for controlling requests of a processing unit. The request controller may include an request controller input for receiving an request and an request processing unit connected to the request controller input. The request may request to switch a context of said processing unit or to switch the processing unit from a current an operation to another operation. The request processing unit may decide on the request based on a decision criterion. An request controller output may be connected to the request processing unit, for outputting information about at least granted request request. The request processing unit may include a control logic unit including: a state input for receiving information about a current state of a system including the processing unit; and a request input for receiving information about a received request request.Type: ApplicationFiled: February 16, 2007Publication date: February 4, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Vladimir A. Litovtchenko, Florian Bogenberger
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Publication number: 20100011142Abstract: A request controller for controlling processing of requests by one or more semiconductor data processing unit. The resource controller includes a controller input for receiving a request for the processing unit to switch a context of the processing unit or to switch the processing unit from a current an operation to another operation. The resource controller includes a resource budget memory in which one or more budget value can be stored. The budget value represents an amount of a resource of the processing unit. The resource controller further has a budget controller which includes a first budget controller input connected to the request controller input. A second budget controller input is connected to the memory. A comparator is connected to the first budget controller input and the second controller input, for comparing a consumption value associated with the request with the budget value.Type: ApplicationFiled: February 8, 2007Publication date: January 14, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Florian Bogenberger, Vladimir A. Litovtchenko
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Publication number: 20100001770Abstract: A data communication network may include two or more master clocks, and a synchronisation system connected to the master clocks. The synchronisation system may determine a time-base for the master clocks. The synchronisation system may control the master clocks according to the determined time-base. The data communication network may include one or more slave clocks. The slave clocks may be controlled by a slave clock time-base controller based on time information of a single selected master clock selected from the master clocks.Type: ApplicationFiled: May 14, 2007Publication date: January 7, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Florian Bogenberger, Mathias Rausch
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Patent number: 7586953Abstract: The invention refers to a method for monitoring a communication media access schedule of a communication controller (5) of a communication system (1) by means of a bus guardian (6). The communication system (1) comprises a communication media (2) and nodes (3) connected to the communication media (2). Each node (3) comprises a communication controller (5) and a bus guardian (6) assigned to the communication controller (5). Messages are transmitted among the nodes (3) across the communication media (2) based on a cyclic time triggered communication media access scheme.Type: GrantFiled: July 7, 2003Date of Patent: September 8, 2009Assignees: Robert Bosch GmbH, Bayerische Motoren Werke AG, DaimlerChrysler AG, Freescale Semiconductor, Inc., GM Global Technology Operations, Inc., NXP B.V.Inventors: Thomas Forest, Bernd Hedenetz, Mathias Rausch, Christopher Temple, Harald Eisele, Bernd Elend, Jörn Ungermann, Matthias Kühlewein, Ralf Belschner, Peter Lohrmann, Florian Bogenberger, Thomas Wuerz, Arnold Millsap, Patrick Heuts, Robert Hugel, Thomas Führer, Bernd Müller, Florian Hartwich, Manfred Zinke, Josef Berwanger, Christian Ebner, Harald Weiler, Peter Fuhrmann, Anton Schedl, Martin Peller
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Publication number: 20090150720Abstract: A data processing system includes a processor having a multi-way cache which has a first and a second way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a memory, where the processor, in response to a read address missing in the cache, provides the read address to the memory. The second way may be dynamically configured to be redundant to the first way during operation of the processor in response to an error detection signal. In one aspect, when the second way is configured to be redundant, in response to the read address hitting in the cache, data addressed by an index portion of the read address is provided from both the first and second way and compared to each other to determine if a comparison error exists.Type: ApplicationFiled: December 6, 2007Publication date: June 11, 2009Inventors: Jehoda Rafaeli, Florian Bogenberger, James B. Eifert
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Patent number: 7430261Abstract: A method and a bit stream decoding unit for bit stream decoding has a bit stream comprising a number of consecutive samples. In order to provide for rapid and, in particular, reliable decoding of the bit stream, a detection window comprising a number of samples is defined and the detection window is positioned at certain positions on the bit stream in order to comprise certain samples with respective sample values. A majority voting is applied to the sample values in the detection window and, in dependence on the result of the majority voting, the bit stream is decoded and respective bit values are generated.Type: GrantFiled: July 7, 2003Date of Patent: September 30, 2008Assignees: Robert Bosch GmbH, DaimlerChrysler AG, Bayerische Motoren Werke AG, General Motors Corp., Motorola Inc., Koninklijke Philips Electronics N.V.Inventors: Thomas Forest, Bernd Hedenetz, Mathias Rausch, Christopher Temple, Harald Eisele, Bernd Elend, Jörn Ungermann, Matthias Kühlewein, Ralf Belschner, Peter Lohrmann, Florian Bogenberger, Thomas Wuerz, Arnold Millsap, Patrick Heuts, Robert Hugel, Thomas Führer, Bernd Müller, Florian Hartwich, Manfred Zinke, Josef Berwanger, Christian Ebner, Harald Weiler, Peter Fuhrmann, Anton Schedl, Martin Peller
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Publication number: 20060045133Abstract: A multi-node communications system is provided with communications protocol using both static (11, 12, 13, 18) (pre-determined) and dynamic (51, 52, 53 . . . ) (run-time determined) consecutive communication slots is used. The system has a number of distributed communication nodes, each node being arranged for communicating frames of data with the other nodes during both the static (11, 12, 13 . . . ) and the dynamic (51, 52, 53 . . . ) communication slots. Each node includes a synchronized time base 5 made up of consecutive timeslots (11, 12, 13 . . . , 51, 52, 53 . . . ). The timebase 5 has substantially the same error tolerance in each node. For static communication (10), a predetermined number of timeslots (20) are utilized for each static communication slot. For dynamic communication a dynamically allocated number of timeslots (60) are utilized for each dynamic communication slot. In this way both static and dynamic media arbitration is provided within a periodically recurring communication pattern.Type: ApplicationFiled: November 21, 2003Publication date: March 2, 2006Applicant: Freescale Semiconductor, Inc.Inventors: Christopher Temple, Florian Bogenberger, Mathias Rausch, Manfred Thanner, Thomas Wuerz, Leonard Link
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Publication number: 20050141565Abstract: The invention refers to one of a number of nodes of a communication system. The nodes are connected to a communication media for transmitting data among the nodes. Said one node comprises a communication controller, across which the node is connected to the communication media, and a bus guardian for controlling access of the communication controller to the communication media. In order to provide a cheap but nevertheless reliable way for monitoring the synchronized clock signal of a node of a communication system and in particular for detecting deviations of the synchronized clock signal it is suggested that a synchronized clock signal from the communication controller is made available to the bus guardian, and that the bus guardian comprises means for monitoring the synchronized clock signal using a bus guardian internal clock signal, which is generated by means of an electronic circuit and which is less accurate than the synchronized clock signal to be monitored.Type: ApplicationFiled: July 7, 2003Publication date: June 30, 2005Applicants: Robert Bosch GmbH, Daimler Chrysler AG, Bayerische Motoren Werke AG, General Motors Corp., Motorola Inc., Koninklijke Philips Electronics N.V.Inventors: Thomas Forest, Bernd Hedenetz, Mathias Rausch, Christopher Temple, Harald Eisele, Bernd Elend, Jorn Ungermann, Matthias Kuhlewein, Ralf Belschner, Peter Lohrmann, Florian Bogenberger, Thomas Wuerz, Arnold Millsap, Patrick Heuts, Robert Hugel, Thomas Fuhrer, Bernd Muller, Florian Hartwich, Manfred Zinke, Josef Berwanger, Christian Ebner, Harald Weiler, Peter Fuhrmann, Anton Schedl, Martin Peller
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Publication number: 20040090962Abstract: A method and a bit stream decoding unit for bit stream decoding has a bit stream comprising a number of consecutive samples. In order to provide for rapid and, in particular, reliable decoding of the bit stream, a detection window comprising a number of samples is defined and the detection window is positioned at certain positions on the bit stream in order to comprise certain samples with respective sample values. A majority voting is applied to the sample values in the detection window and, in dependence on the result of the majority voting, the bit stream is decoded and respective bit values are generated.Type: ApplicationFiled: July 7, 2003Publication date: May 13, 2004Applicant: Robert Bosch GmbH,Inventors: Thomas Forest, Bernd Hedenetz, Mathias Rausch, Christopher Temple, Harald Eisele, Bernd Elend, Jorn Ungermann, Matthias Kuhlewein, Ralf Belschner, Peter Lohrmann, Florian Bogenberger, Thomas Wuerz, Arnold Millsap, Patrick Heuts, Robert Hugel, Thomas Fuhrer, Bernd Muller, Florian Hartwich, Manfred Zinke, Josef Berwanger, Christian Ebner, Harald Weiler, Peter Fuhrmann, Anton Schedl, Martin Peller
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Publication number: 20040081193Abstract: Method for transmitting data within a communication system, the communication system comprising a communication media and a number of nodes connected to the communication media, the data being transmitted across the communication media within a communication cycle comprising a number of time slots assigned to one or more nodes of the communication system. In order to provide a possibility for a data transmission within communication cycles, which can satisfy the demands in communication systems for safety critical applications, too, it is suggested, that the communication cycle is initiated by an external event. The external event can be caused by manually setting a bit by a host, by a configurable timer in a controller host interface (CHI) or by an external trigger.Type: ApplicationFiled: July 7, 2003Publication date: April 29, 2004Inventors: Thomas Forest, Bernd Hedenetz, Mathias Rausch, Christopher Temple, Harald Eisele, Bernd Elend, Jorn Ungermann, Matthias Kuhlewein, Ralf Belschner, Peter Lohrmann, Florian Bogenberger, Thomas Wuerz, Arnold Millsap, Patrick Heuts, Robert Hugel, Thomas Fuhrer, Bernd Muller, Florian Hartwich, Manfred Zinke, Josef Berwanger, Christian Ebner, Harald Weiler, Peter Fuhrmann, Anton Schedl, Martin Peller
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Publication number: 20040081079Abstract: The invention refers to a method for monitoring a communication media access schedule of a communication controller (5) of a communication system (1) by means of a bus guardian (6). The communication system (1) comprises a communication media (2) and nodes (3) connected to the communication media (2). Each node (3) comprises a communication controller (5) and a bus guardian (6) assigned to the communication controller (5). Messages are transmitted among the nodes (3) across the communication media (2) based on a cyclic time triggered communication media access scheme.Type: ApplicationFiled: July 7, 2003Publication date: April 29, 2004Applicants: Robert Bosch GmbH, Daimler Chrysler AG, Bayerische Motoren Werke AG, General Motors Corp, Motorola Inc., Koninklijke Philips Electronics N. V.Inventors: Thomas Forest, Bernd Hedenetz, Mathias Rausch, Christopher Temple, Harald Eisele, Bernd Elend, Jorn Ungermann, Matthias kuhlewein, Ralf Belschner, Peter Lohrmann, Florian Bogenberger, Thomas Wuerz, Arnold Millsap, Patrick Heuts, Robert Hugel, Thomas Fuhrer, Bernd Muller, Florian Hartwich, Manfred Zinke, Josef Berwanger, Christian Ebner, Harald Weiler, Peter Fuhrmann, Anton Schedl, Martin Peller