Patents by Inventor Florian Herrault

Florian Herrault has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11940495
    Abstract: An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: March 26, 2024
    Assignee: PseudolithIC, Inc.
    Inventors: James Buckwalter, Michael Hodge, Justin Kim, Daniel Green, Florian Herrault
  • Patent number: 11810876
    Abstract: An electronic assembly has a host wafer having a first circuit including passive devices for the purpose of one of tuning or matching networks. Chiplets are placed in the cavities. At least one chiplet has a second circuit including at least one transistor or switch device and passive tuning circuits including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network. Electrical interconnects between the chiplets and wafer electrically connect the first circuitry to the second circuitry.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: November 7, 2023
    Assignee: PseudolithIC, Inc.
    Inventors: James Buckwalter, Michael Hodge, Justin Kim, Florian Herrault, Daniel Green
  • Patent number: 11756848
    Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: September 12, 2023
    Assignee: PseudolithIC, Inc.
    Inventors: Florian Herrault, Isaac Rivera, Daniel S. Green, James F. Buckwalter
  • Patent number: 11733297
    Abstract: An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: August 22, 2023
    Assignee: PseudolithIC, Inc.
    Inventors: James Buckwaiter, Michael Hodge, Justin Kim, Daniel Green, Florian Herrault
  • Publication number: 20230122242
    Abstract: An electronic assembly, having a carrier wafer with a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising first and second integrated circuit contact pads; said carrier wafer comprising a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface; first and second component chips held in said through-wafer cavity each by direct contact of at least a side surface of said first and second component chips with a heat conducting attachment material that fills said through-wafer cavity; said first and second component chips comprising respectively at least a first and a second component contact pads; a barrier having a heat conductivity lower than a heat conductivity of said carrier wafer held by said heat conducting attachment material in said through-wafer cavity between said first and said second component chips.
    Type: Application
    Filed: August 15, 2022
    Publication date: April 20, 2023
    Inventor: Florian Herrault