Patents by Inventor Florian Longnos
Florian Longnos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11886333Abstract: A memory block reclamation method includes, after receiving an unmap command sent by a memory controller, a medium controller reclaims one or more memory blocks in a non-volatile memory connected to the medium controller based on memory logical address information in the unmap command. The one or more reclaimed memory blocks are available memory blocks.Type: GrantFiled: March 31, 2023Date of Patent: January 30, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Florian Longnos, Wei Yang
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Patent number: 11853608Abstract: An information writing method is applied to an non-volatile dual in-line memory module (NVDIMM), the NVDIMM includes an NVDIMM controller and a non-volatile memory (NVM), and the method includes receiving, by the NVDIMM controller, a sanitize command from a host, where the sanitize command is used to instruct the NVDIMM controller to sanitize data in the NVM using a first write pattern, and the first write pattern is one of at least two patterns of writing information into the NVM, and writing, by the NVDIMM controller, information into the NVM according to the sanitize command.Type: GrantFiled: December 22, 2021Date of Patent: December 26, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Florian Longnos, Feng Yang, Wei Yang
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Publication number: 20230325311Abstract: A memory block reclamation method includes, after receiving an unmap command sent by a memory controller, a medium controller reclaims one or more memory blocks in a non-volatile memory connected to the medium controller based on memory logical address information in the unmap command. The one or more reclaimed memory blocks are available memory blocks.Type: ApplicationFiled: March 31, 2023Publication date: October 12, 2023Inventors: Florian Longnos, Wei Yang
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Patent number: 11784756Abstract: A memory access technology and a computer system, where the computer system includes a memory controller and a medium controller connected to the memory controller. In the computer system, when detecting that an error occurs in first data that is returned by the medium controller in response to a first send command, the memory controller determines sequence information of the first send command in a plurality of send commands that have been sent by the memory controller within a time period from a time point at which the first send command is sent to a current time, and sends a data retransmission command to the medium controller to instruct the medium controller to resend the first data based on the sequence information.Type: GrantFiled: June 5, 2020Date of Patent: October 10, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Shihai Xiao, Florian Longnos, Feng Yang
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Patent number: 11681452Abstract: A computer system includes a memory controller and a non-volatile dual in-line memory module (NVDIMM) connected to the memory controller. The NVDIMM comprises a non-volatile memory (NVM) for storing data and a media controller. After receiving a read command for reading first data stored in the NVDIMM from the memory controller, the media controller reads multiple data subblocks of the first data from the NVM. After sending multiple ready signals to notify the memory controller that multiple data subblocks of the first data are available, the media controller receives multiple send commands for fetching the multiple data subblocks. The media controller then transmits to the memory controller the multiple data subblocks in response to the multiple send commands.Type: GrantFiled: January 6, 2022Date of Patent: June 20, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Shihai Xiao, Florian Longnos, Wei Yang
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Patent number: 11521674Abstract: A memory access method and a computer system are provided. According to the memory access method, whether to flip the to-be-stored data for storage may be determined based on quantities of “1” and “0” in data to be written into a dynamic random access memory (DRAM) and a storage mode of the DRAM, to reduce a quantity of storage cells with high electric charges in the DRAM, thereby reducing a data error probability.Type: GrantFiled: March 30, 2021Date of Patent: December 6, 2022Assignee: Huawei Technologies Co., Ltd.Inventors: Kraft Kira, Mathew Deepak, Chirag Sudarshan, Jung Matthias, Weis Christian, Norbert Wehn, Florian Longnos, Gezi Li, Wei Yang
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Publication number: 20220206686Abstract: A computer system includes a memory controller and a non-volatile dual in-line memory module (NVDIMM) connected to the memory controller. The NVDIMM comprises a non-volatile memory (NVM) for storing data and a media controller. After receiving a read command for reading first data stored in the NVDIMM from the memory controller, the media controller reads multiple data subblocks of the first data from the NVM. After sending multiple ready signals to notify the memory controller that multiple data subblocks of the first data are available, the media controller receives multiple send commands for fetching the multiple data subblocks. The media controller then transmits to the memory controller the multiple data subblocks in response to the multiple send commands.Type: ApplicationFiled: January 6, 2022Publication date: June 30, 2022Inventors: Shihai Xiao, Florian Longnos, Wei Yang
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Publication number: 20220188037Abstract: An information writing method is applied to an non-volatile dual in-line memory module (NVDIMM), the NVDIMM includes an NVDIMM controller and a non-volatile memory (NVM), and the method includes receiving, by the NVDIMM controller, a sanitize command from a host, where the sanitize command is used to instruct the NVDIMM controller to sanitize data in the NVM using a first write pattern, and the first write pattern is one of at least two patterns of writing information into the NVM, and writing, by the NVDIMM controller, information into the NVM according to the sanitize command.Type: ApplicationFiled: December 22, 2021Publication date: June 16, 2022Inventors: Florian Longnos, Feng Yang, Wei Yang
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Patent number: 11289159Abstract: A memory device includes a storage unit array and a controller. The storage unit array contains storage units arranged in M rows and N columns and has M word lines and N bit line pairs. Each of the N bit line pairs includes a bit line and a source line. In operation, after obtaining Q rows of data that are to be written into Q rows of storage units in the storage unit array, the controller writes a first value into each of storage units in a column j in P columns of storage units. The controller then determines to-be-written rows in the Q rows of data, and writes in parallel a second value into each of storage units of the to-be-written rows in the storage units in the column j.Type: GrantFiled: December 19, 2019Date of Patent: March 29, 2022Assignee: Huawei Technologies Co., Ltd.Inventors: Florian Longnos, Engin Ipek, Shihai Xiao
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Patent number: 11237762Abstract: An information writing method is applied to an non-volatile dual in-line memory module (NVDIMM), the NVDIMM includes an NVDIMM controller and a non-volatile memory (NVM), and the method includes receiving, by the NVDIMM controller, a sanitize command from a host, where the sanitize command is used to instruct the NVDIMM controller to sanitize data in the NVM using a first write pattern, and the first write pattern is one of at least two patterns of writing information into the NVM, and writing, by the NVDIMM controller, information into the NVM according to the sanitize command.Type: GrantFiled: February 28, 2020Date of Patent: February 1, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Florian Longnos, Feng Yang, Wei Yang
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Patent number: 11231864Abstract: A computer system includes a memory controller and a non-volatile dual in-line memory module (NVDIMM) connected to the memory controller. The NVDIMM comprises a non-volatile memory (NVM) for storing data and a media controller. After receiving a read command for reading first data stored in the NVDIMM from the memory controller, the media controller reads multiple data subblocks of the first data from the NVM. After sending multiple ready signals to notify the memory controller that multiple data subblocks of the first data are available, the media controller receives multiple send commands for fetching the multiple data subblocks. The media controller then transmits to the memory controller the multiple data subblocks in response to the multiple send commands.Type: GrantFiled: July 13, 2020Date of Patent: January 25, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Shihai Xiao, Florian Longnos, Wei Yang
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Publication number: 20210217464Abstract: A memory access method and a computer system are provided. According to the memory access method, whether to flip the to-be-stored data for storage may be determined based on quantities of “1” and “0” in data to be written into a dynamic random access memory (DRAM) and a storage mode of the DRAM, to reduce a quantity of storage cells with high electric charges in the DRAM, thereby reducing a data error probability.Type: ApplicationFiled: March 30, 2021Publication date: July 15, 2021Inventors: Kraft KIRA, Mathew DEEPAK, Chirag SUDARSHAN, Jung MATTHIAS, Weis CHRISTIAN, Norbert WEHN, Florian LONGNOS, Gezi LI, Wei YANG
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Patent number: 10997078Abstract: A method for accessing a non-volatile memory comprises that an NVM controller receive a first access request from a processor and determines whether the first access request is used to access a page table. If the first access request is used to access the page table, the NVM controller obtains an AIT entry by reading a page table entry indicated by the first address information and caches the AIT entry to an AIT cache. The NVM controller monitors access of the processor to the page table, prefetches the to-be-accessed AIT entry.Type: GrantFiled: June 27, 2019Date of Patent: May 4, 2021Assignee: Huawei Technologies Co., Ltd.Inventors: Shihai Xiao, Lei Fang, Florian Longnos
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Publication number: 20200393965Abstract: A computer system includes a memory controller and a non-volatile dual in-line memory module (NVDIMM) connected to the memory controller. The NVDIMM comprises a non-volatile memory (NVM) for storing data and a media controller. After receiving a read command for reading first data stored in the NVDIMM from the memory controller, the media controller reads multiple data subblocks of the first data from the NVM. After sending multiple ready signals to notify the memory controller that multiple data subblocks of the first data are available, the media controller receives multiple send commands for fetching the multiple data subblocks. The media controller then transmits to the memory controller the multiple data subblocks in response to the multiple send commands.Type: ApplicationFiled: July 13, 2020Publication date: December 17, 2020Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Shihai XIAO, Florian LONGNOS, Wei YANG
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Patent number: 10807301Abstract: Method for manufacturing a mechatronic system comprising: a step of manufacturing a mechanical structure (SM) by three-dimensional printing by fused filament deposition of at least one first electrically insulating material (M1), and a step of manufacturing at least one electrical component (CE) in contact with at least one element of said mechanical structure and secured therewith; characterized in that said step of manufacturing at least one electrical component is implemented by three-dimensional printing by fused filament deposition of at least one second material (M2), conductive or resistive, directly in contact with said element of the mechanical structure. Apparatus for implementing such a method. Mechatronic system that can be manufactured by such a method.Type: GrantFiled: June 5, 2017Date of Patent: October 20, 2020Assignees: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE PARIS-SUDInventors: Mehdi Ammi, Florian Longnos
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Publication number: 20200304238Abstract: A memory access technology and a computer system, where the computer system includes a memory controller and a medium controller connected to the memory controller. In the computer system, when detecting that an error occurs in first data that is returned by the medium controller in response to a first send command, the memory controller determines sequence information of the first send command in a plurality of send commands that have been sent by the memory controller within a time period from a time point at which the first send command is sent to a current time, and sends a data retransmission command to the medium controller to instruct the medium controller to resend the first data based on the sequence information.Type: ApplicationFiled: June 5, 2020Publication date: September 24, 2020Inventors: Shihai Xiao, Florian Longnos, Feng Yang
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Publication number: 20200257620Abstract: A memory block reclamation method and apparatus are provided. According to the method, after receiving an unmap command sent by a memory controller, a medium controller reclaims one or more memory blocks in a non-volatile memory connected to the medium controller based on memory logical address information in the unmap command. The one or more reclaimed memory blocks are available memory blocks.Type: ApplicationFiled: April 30, 2020Publication date: August 13, 2020Inventors: Florian Longnos, Wei Yang
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Patent number: 10732876Abstract: A memory access technology and a computer system, where the computer system includes a memory controller, a media controller, and a non-volatile memory (NVM) coupled to the media controller. After receiving a first read command from the memory controller, the media controller may read first data from the NVM based on a first address in the first read command. Then the media controller transmit, to the memory controller, at least two fixed-length data subblocks and metadata of the at least two data subblocks in response to at least two first send commands received from the memory controller. The metadata includes a location identifier indicating an offset of a corresponding data subblock in the first data. Thus, the memory controller obtains the first data based on the at least two data subblocks and location identifiers in the metadata.Type: GrantFiled: February 25, 2019Date of Patent: August 4, 2020Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Shihai Xiao, Florian Longnos, Wei Yang
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Publication number: 20200201577Abstract: An information writing method is applied to an non-volatile dual in-line memory module (NVDIMM), the NVDIMM includes an NVDIMM controller and a non-volatile memory (NVM), and the method includes receiving, by the NVDIMM controller, a sanitize command from a host, where the sanitize command is used to instruct the NVDIMM controller to sanitize data in the NVM using a first write pattern, and the first write pattern is one of at least two patterns of writing information into the NVM, and writing, by the NVDIMM controller, information into the NVM according to the sanitize command.Type: ApplicationFiled: February 28, 2020Publication date: June 25, 2020Inventors: Florian Longnos, Feng Yang, Wei Yang
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Publication number: 20200126618Abstract: A memory device includes a storage unit array and a controller. The storage unit array contains storage units arranged in M rows and N columns and has M word lines and N bit line pairs. Each of the N bit line pairs includes a bit line and a source line. In operation, after obtaining Q rows of data that are to be written into Q rows of storage units in the storage unit array, the controller writes a first value into each of storage units in a column j in P columns of storage units. The controller then determines to-be-written rows in the Q rows of data, and writes in parallel a second value into each of storage units of the to-be-written rows in the storage units in the column j.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Florian Longnos, Engin Ipek, Shihai Xiao