Abstract: The present description concerns a random number generation circuit (2) of correlated sampling ring oscillator type comprising: two identical ring oscillators (RO1, R02) implemented in CMOS-on-FDSOI technology; a circuit (104) sampling and storing an output (O1) of one of the two oscillators (RO1) at a frequency of the other one of the two oscillators (R02) and delivering a corresponding binary signal (Beat); and a circuit (200) controlling back gates of PMOS and NMOS transistors of at least one delay element of at least one of the two oscillators (RO1, R02) based on a period difference between the two oscillators (RO1, R02).

Abstract: A random number generator including at least one ring oscillator comprising at least one inverter formed by at least two FDSOI LVT transistors, one being of the NMOS type and the other one being of the PMOS type, and further including a circuit for applying voltages on rear gates of the transistors configured to bias the transistors in the FBB mode.

Abstract: A microelectronic device and method for manufacturing a microelectronic device comprising a plurality of resistive memories, a part of these resistive memories, called PUF memories, forming a PUF, the rest of these resistive memories being known as storage memories. The manufacturing process comprising forming a dielectric layer having on at least one contact surface in contact with an electrode a surface roughness of said surface greater than that of the same dielectric layer of the storage memories.

Abstract: A method for manufacturing a microelectronic device including resistive memory points, a first portion of the memory points forming a physical unclonable function, the memory points of the first portion forming a PUF zone, a second portion of the memory points providing a memory function, the memory points of the second forming a memory zone, the method including providing a support including a first electrode layer and an active oxide resistive memory layer; etching the active oxide resistive memory layer in the PUF zone; etching the active oxide resistive memory layer in the memory zone, the etching in the memory zone producing a dispersion of roughness of the oxide layer less than the dispersion of roughness produced by the etching in the PUF zone; depositing a second electrode layer; etching the second electrode layer, the active oxide layer and the first electrode layer to define the memory points.

Abstract: A method for securing an integrated circuit upon making it includes the steps of delimiting said integrated circuit into a first so-called standard zone and into a second so-called security zone, and randomly misaligning in said security zone between a lower level of interconnection holes and an upper level of interconnection holes generating the formation of an interconnection structure having a random distribution of electrical contact and non-contact points. Also described is a secured integrated circuit obtainable using such a method.

Abstract: The invention relates to a method of securing an integrated circuit during its fabrication on a wafer, said method including the following steps: delimitation of said wafer of the integrated circuit (1) into a first zone called a standard zone (5a) and a second zone called a security zone (5b), and creation of a random connection tracks network (7b) in said security zone (5b) configured to interconnect a set of conducting nodes (9b) thus forming a physical unclonable function modelled by random electrical continuity that can be queried through said set of conducting nodes using a challenge-response authentication protocol.

Abstract: A microelectronic device and method for manufacturing a microelectronic device comprising a plurality of resistive memories, a part of these resistive memories, called PUF memories, forming a PUF, the rest of these resistive memories being known as storage memories. The manufacturing process comprising forming a dielectric layer having on at least one contact surface in contact with an electrode a surface roughness of said surface greater than that of the same dielectric layer of the storage memories.

Abstract: An integrated circuit and a method of securing the integrated circuit during its fabrication. The method includes delimitation of the integrated circuit into a first zone called a standard zone and a second zone called a security zone, and random degradation of an interconnection structure of the security zone thus forming a physical unclonable function modelled by random electrical continuity that can be queried by a challenge-response authentication protocol.

Abstract: A method for securing an integrated circuit upon making it includes the of delimiting said integrated circuit into a first so-called standard zone and into a second so-called security zone, and randomly misaligning in said security zone between a lower level of interconnection holes and an upper level of interconnection holes generating the formation of an interconnection structure having a random distribution of electrical contact and non-contact points. Also described is a secured integrated circuit obtainable using such a method.

Abstract: A method of encrypting a program instructions stream and a method of executing an instructions stream thus encrypted. Instructions are translated into binary code before being encrypted by a stream cipher method. When the program contains a conditional or unconditional branch instruction, an instruction is inserted in the program to initialize the pseudo-random sequence generator using an initialization vector, the initialization vector being used to generate the pseudo-random sequence for encryption and decryption of instructions at the branch address. Instructions can be decrypted and executed on-the-fly without needing to know their physical addresses, even in the presence of a branch.

Abstract: The invention relates to a method of securing an integrated circuit during its fabrication on a wafer, said method including the following steps: delimitation of said wafer of the integrated circuit (1) into a first zone called a standard zone (5a) and a second zone called a security zone (5b), and creation of a random connection tracks network (7b) in said security zone (5b) configured to interconnect a set of conducting nodes (9b) thus forming a physical unclonable function modelled by random electrical continuity that can be queried through said set of conducting nodes using a challenge-response authentication protocol.

Abstract: An integrated circuit and a method of securing the integrated circuit during its fabrication. The method includes delimitation of the integrated circuit into a first zone called a standard zone and a second zone called a security zone, and random degradation of an interconnection structure of the security zone thus forming a physical unclonable function modelled by random electrical continuity that can be queried by a challenge-response authentication protocol.

Abstract: A method for encrypting a message by a host device includes requesting, by the host device, a message key from a secure device and generating, by the secure device, the message key using a secret key stored in the secure device and which is not communicated to the host device. The method further includes the prior steps of requesting, by the host device, a token from the secure device and generating the token by the secure device, and transmitting the token to the host device. The requesting, by the host device, of the message key includes transmitting the token. The generating, by the secure device, of the message key is preceded by checking the legitimacy of the token.

Abstract: A method of encrypting a program instructions stream and a method of executing an instructions stream thus encrypted. Instructions are translated into binary code before being encrypted by a stream cipher method. When the program contains a conditional or unconditional branch instruction, an instruction is inserted in the program to initialise the pseudo-random sequence generator using an initialisation vector, the initialisation vector being used to generate the pseudo-random sequence for encryption and decryption of instructions at the branch address. Instructions can be decrypted and executed on-the-fly without needing to know their physical addresses, even in the presence of a branch.

Abstract: A method for encrypting a message by a host device includes requesting, by the host device, a message key from a secure device and generating, by the secure device, the message key using a secret key stored in the secure device and which is not communicated to the host device. The method further includes the prior steps of requesting, by the host device, a token from the secure device and generating the token by the secure device, and transmitting the token to the host device. The requesting, by the host device, of the message key includes transmitting the token. The generating, by the secure device, of the message key is preceded by checking the legitimacy of the token.

Abstract: The present invention relates to a method for equalizing modulation symbols transmitted on a non-linear transmission channel. The equalizing method operates on a sequence of observables, each non-linearly depending on a predetermined number of consecutive modulation symbols, and is based on a Viterbi algorithm. It comprises a prior step of receiving a pilot sequence of modulation symbols and storing corresponding observables (110), said pilot sequence leading to a path passing through all the branches of the lattice. In a second step (120), for each symbol to be equalized, for each branch, a branch metric is calculated as a distance between the observable corresponding to the modulation symbol to be equalized and the observable stored for said branch.

Abstract: A method for phase modulation of a carrier signal from a transmitter to a contactless transponder in which data is coded as consecutive symbols, each corresponding to a predefined number of carrier cycles, and in which a symbol time is at least two cycles of the carrier signal includes, at the transmitter, spreading a phase jump of a symbol in relation to a preceding symbol over a first part of the symbol time. The establishment of the phase jump is completed in the first part of the symbol time. The periods of the cycles are constant during a second part of the symbol time.

Abstract: The present invention relates to a digital modulation method and a corresponding modulator. The modulator comprises a transcoder (110) followed by a FIFO register (120) and a 2-PSK modulator (130). The transcoder codes a binary word of fixed size into a code word of variable size using a transcoding table. The transcoding table codes at least one first binary word, leading to a first number of phase transitions at the output of the modulator, into a second word of size greater than that of the first word, leading to, at the output of the modulator, a second number of phase transitions less than the first number of phase transitions.

Abstract: The invention relates to a method for encoding contactless communication data from a transponder to a reader via charge modulation, in the form of a set of modulation patterns, each modulation pattern being a series of charge levels of a predefined length used for physical encoding, having a duration of n carrier periods (Tc), including a series of at least two charge levels, having a minimum pulse width (w) corresponding to the shortest duration of a single charge level in the pattern, and having a retromodulation rate (t) corresponding to the ratio between the retromodulation time and the duration of a pattern, characterized in that the number (k) of patterns is greater than four, the minimum pulse widths (w) of at least two patterns are different, and the retromodulation rates (t) of at least two patterns are different. The invention also relates to a device for implementing the method.

Abstract: The present invention relates to a method for equalizing modulation symbols transmitted on a non-linear transmission channel. The equalizing method operates on a sequence of observables, each non-linearly depending on a predetermined number of consecutive modulation symbols, and is based on a Viterbi algorithm. It comprises a prior step of receiving a pilot sequence of modulation symbols and storing corresponding observables (110), said pilot sequence leading to a path passing through all the branches of the lattice. In a second step (120), for each symbol to be equalized, for each branch, a branch metric is calculated as a distance between the observable corresponding to the modulation symbol to be equalized and the observable stored for said branch.