Abstract: The stable memory (2) includes an interface (30) for communication with an allocated processor (1). It includes two memory banks (51, 52) for containing the same information at each address. The interface (b 30) interchanges addresses and commands with the memory banks via an access logic conroller or filter (20). Data interchanges pass via a switching and comparator member (40). The information contained in the memory banks (51, 52) is structured in the form of objects which are rendered indivisible by use of a chaining vector which is established and verified by the logic controller (20).

Abstract: An apparatus and method for fast and stable information storage is provided that employs a data storage apparatus having a series of non-volatile memory banks that are externally addressable and have selective write and read controls. Access to the memory banks is provided via hardware access protection mechanisms to ensure that any access to the memory banks is verified by means of an access key. Software access protection is also provided if two separate processors share a common memory bank.