Abstract: An oversampling delta-sigma analog-to-digital converter suitable for single-cycle operation is provide. In a preferred embodiment of the present invention, only one multiply-accumulate processor is present in the digital filtering stage for decimating the output sequence R(I). A system controller produces precisely timed modulator enable (EnM) and digital filter enable (EnF) signals for coordinating activation of certain circuit elements and for managing power consumption of the system.

Abstract: An oversampling data converter with good rejection capability is provided. The oversampling data converter includes three primary parts; a delta-sigma modulator for sampling and digitizing incoming analog signals, a high order digital filter for discarding unwanted frequency components, and an internal clock generator for controlling the operation of the modulator and the filter. All three primary parts are provided in the same package and also on the same die. No frequency-setting external components are necessary. The high order digital filter provides more than 100 dB rejection at a first null frequency. The first null provided by the filter has a sufficiently broad range so as to allow a low accuracy internal clock generator to be used. If necessary, the clock can be generated externally or from some other part of the system.

Abstract: The invention provides methods and apparatus for improving the full-scale accuracy of an oversampling analog-to-digital converter. In particular, an improved switched-capacitor subtractor/integrator circuit is described that effectively provides a desired capacitor ratio by using N+M distinct unit capacitors that each sample an input signal a first predetermined number of times and sample one or more reference signals a second predetermined number of times, where the ratio of the first predetermined number to the second predetermined number is the desired capacitor ratio N/M.

Abstract: The power management system tracks the total amount of power drawn from a bus by devices connected to the bus and to the bus itself, based on the individual operational status of each device. The power manager system also tracks the total amount of power supplied to the bus. From this information the power manager system determines whether a power surplus exists sufficient to allow an additional device to operate or to allow a currently operating device to draw more power. Power usage requests received from devices connected to the bus are granted or denied by the power management system based on the determination of available power. The power management system additionally is capable of sequencing the use of several devices to allow the devices to each operate while maintaining the total power draw within an acceptable range. The system provides for efficient use of a limited amount of power to allow operation of more devices than conventionally allowed with a bus.

Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme.

Abstract: A system and method are described which take an arbitrarily assembled collection of nodes on a bus or network and imposes an optimized hierarchical tree structure where there is only one root node. Nodes having both parent and child nodes are considered branch nodes while nodes having only parent nodes are leaf nodes. Loops or cycles in the physical topology are resolved into a logical topology that is acyclic and directed. A signaling scheme is developed in which nodes, via on board communications hardware, signal all connected nodes and respond accordingly until hierarchical relationships are established. Cycles are resolved by intelligently breaking links to yield an acyclic graph. Direction is established by each node recognizing its parent/child status with respect to connected nodes until a single node is established as a root node.

Abstract: A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port in the node includes a bus driver that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus. A terminator circuit is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus, which is coupled to the plurality of ports for transmission. A biasing circuit for the bus drivers allows operation at low voltages, and furthermore insures the zero crossing of the differential voltage signal on the second differential bus.

Abstract: The power management system tracks the total amount of power drawn from a bus by devices connected to the bus and to the bus itself, based on the individual operational status of each device. The power manager system also tracks the total amount of power supplied to the bus. From this information the power manager system determines whether a power surplus exists sufficient to allow an additional device to operate or to allow a currently operating device to draw more power. Power usage requests received from devices connected to the bus are granted or denied by the power management system based on the determination of available power. The power management system additionally is capable of sequencing the use of several devices to allow the devices to each operate while maintaining the total power draw within an acceptable range. The system provides for efficient use of a limited amount of power to allow operation of more devices than conventionally allowed with a bus.

Abstract: A CMOS differential twisted-pair driver which utilizes CMOS switches and current sources advantageously. No alternative power supply is required, the switches do not have to be low impedance and the device is low power. The preferred embodiment driver further limits signal overshoot and common mode energy. The signal transmission facility is bi-directional so an off state is provided. It is doubly terminated to provide for symmetry, improved bandwidth and reduces reflective signal noise. The double termination also provides for faster rise and fall times which reduces the systems sensitivity to receiver offset.

Abstract: A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme.

Abstract: The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the chock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 2 -nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal.

Abstract: In a driver circuit for a twisted pair cable, a compensator for preventing appreciable common mode current flow into or out of the twisted pair cable in response to the device receiving a wide range of common mode voltage bias levels. A wide range of external bias voltages may be received as a result of variations in the ground node voltages of two coupled devices. The compensator circuit utilizes a feed back loop and monitors the bias voltage received on the twisted pair cable. As the magnitude of the common mode current increases due to external bias voltage variation from a reference bias voltage, the current flow of p-channel transistors, coupled in an arrangement of the present invention, is increased (or decreased, as necessary) so that reduced common mode current flows onto the twisted pair cable. The present invention reduces appreciable common mode current flow through the twisted pair cable from the driver that are due to variations in the external bias voltage between communication devices.

Abstract: A node for a communication system that has a plurality of nodes, each of which may be coupled to a local host. The nodes are coupled between themselves in a tree topology by a plurality of point-to-point links. The interconnected nodes provide a first bus configuration for arbitration like a single bus. Following arbitration, the interconnected nodes provide a second configuration for high speed unidirectional data transfer without the bandwidth limitations of a single bus. Each node includes an arbiter, a data bus, a plurality of ports, a first multiplexer to select either the arbiter or the data bus, and a second multiplexer to select either the arbiter or the data bus. The data bus includes a transmit bus and a receive bus that are coupled with a repeater circuit that can resynchronize the data. During arbitration, the multiplexers select the arbiter to provide the function of a single bus for all the nodes. During data transfer, the multiplexers are configured for transmission of data.

Abstract: In a computer bus arrangement in which a plurality of nodes are interconnected by communication links, control signals are exchanged between the nodes concerning the transmission rate of a data message to be transmitted and the reception rate capability of the nodes. The data message is passed to those nodes which have a reception rate capability which matches or exceeds the transmission rate associated with the message. The other nodes receive a mock data message at a rate within their capability. In order to aid in synchronization within the bus arrangement, the duration of the mock data message is the same as the data message received by the other nodes, even though they are transmitted at different rates.

Abstract: A dynamic, multi-speed bus architecture comprising a plurality of variable speed, fixed size links for coupling a plurality of devices together in an arbitrary network arrangement in which each device coupled to the bus comprises a novel communications node having a scalable interface for enabling the local hosts of the devices to communicate via the multi-speed bus. The interface provided within each node comprises a first module and a second module interconnected via a fixed speed, variable size bus. The first module is coupled to the local host of a device via a fixed speed, fixed size bus for converting a first data packet received from the local host into a second data packet of an appropriate form for transmission on the fixed speed, variable size bus disposed between the two modules. The second module receives the second data packet and converts it into a third data packet of an appropriate form for transmission onto the variable speed, fixed size link coupling the device to the multi-speed bus.

Abstract: The class AB amplifier is configured to provide low quiescent current while achieving high internal switching rates. The buffer is connected to a large external capacitance which provides external compensation. The amplifier includes an input stage which converts differential voltages to current. An output stage provides an output current and also provides a feedback current into the input stage. A biasing network provides voltage for biasing various nodes within the amplifier. Cross-coupling is provided within the output stage for achieving a low quiescent current. A pair of current limiting circuits, one for p-channel element and another for n-channel elements, is also provided.

Abstract: A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port in the node includes a bus driver that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus. A terminator circuit is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus, which is coupled to the plurality of ports for transmission.

Abstract: A mechanism and method for efficiently communicating information regarding particular communication rate ("speed signal") between two or more communication stations (of a communication network). The transmitter operates on the IEEE P1394 High Performance Serial Bus to supply both differential and common mode signaling required by the IEEE standard for exemplary data transfer rates of 100 and 200 Mbit transmission. The present invention includes a transmission circuit that may operate in a differential signal mode and simultaneously in a common mode signal mode both utilizing a twisted pair cable. Data may be transmitted on the twisted pair at small differential signals. Information regarding the signal speed between two coupled units may be simultaneously transmitted using variations in the common mode voltage over the twisted pair. Communication may be initiated at a slower communication rate and then upgraded as appropriate for the two units.

Abstract: A bus interconnect device including port control logic for a communication network having a plurality of multi-port nodes that are connected with point-to-point links. Each node includes a transceiver, turn around logic that controls the transceiver, and a dominant logic physical bus that is coupled to all ports in a node. A bus interconnect device includes a first port, a second port, and a point-to-point link between the first and second ports. During arbitration, from the viewpoint of each node, the bus interconnect devices cause the plurality of physical buses to appear to be a single logical bus having a dominant logic. During data transfer following arbitration, the bus interconnect devices are configured to transmit data from the winning node to all other nodes.

Abstract: The power management system tracks the total amount of power drawn from a bus by devices connected to the bus and to the bus itself, based on the individual operational status of each device. The power manager system also tracks the total amount of power supplied to the bus. From this information the power manager system determines whether a power surplus exists sufficient to allow an additional device to operate or to allow a currently operating device to draw more power. Power usage requests received from devices connected to the bus are granted or denied by the power management system based on the determination of available power. The power management system additionally is capable of sequencing the use of several devices to allow the devices to each operate while maintaining the total power draw within an acceptable range. The system provides for efficient use of a limited amount of power to allow operation of more devices than conventionally allowed with a bus.